ixp425.h
来自「适合KS8695X」· C头文件 代码 · 共 560 行 · 第 1/2 页
H
560 行
/*
* include/asm-arm/arch-ixp425/ixp425.h
*
* Register definitions for IXP425
*
* Copyright (C) 2002 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _ASM_ARM_IXP425_H_
#define _ASM_ARM_IXP425_H_
#define BIT(x) (1<<(x))
/* FIXME: Only this does work for u-boot... find out why... [RS] */
#define UBOOT_REG_FIX 1
#ifdef UBOOT_REG_FIX
# undef io_p2v
# undef __REG
# ifndef __ASSEMBLY__
# define io_p2v(PhAdd) (PhAdd)
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# endif
#endif /* UBOOT_REG_FIX */
/*
*
* IXP425 Memory map:
*
* Phy Phy Size Map Size Virt Description
* =========================================================================
*
* 0x00000000 0x10000000 SDRAM 1
*
* 0x10000000 0x10000000 SDRAM 2
*
* 0x20000000 0x10000000 SDRAM 3
*
* 0x30000000 0x10000000 SDRAM 4
*
* The above four are aliases to the same memory location (0x00000000)
*
* 0x48000000 0x4000000 PCI Memory
*
* 0x50000000 0x10000000 Not Mapped EXP BUS
*
* 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
*
* 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
*
* 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
*
* 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
*
* 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
*/
/*
* SDRAM
*/
#define IXP425_SDRAM_BASE (0x00000000)
#define IXP425_SDRAM_BASE_ALT (0x10000000)
/*
* PCI Configuration space
*/
#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000)
#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Expansion BUS Configuration registers
*/
#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000)
#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000)
#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
/*
* SDRAM configuration registers
*/
#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
/*
* Q Manager space .. not static mapped
*/
#define IXP425_QMGR_BASE_PHYS (0x60000000)
#define IXP425_QMGR_BASE_VIRT (0xFFFDE000)
#define IXP425_QMGR_REGION_SIZE (0x00004000)
/*
* Expansion BUS
*
* Expansion Bus 'lives' at either base1 or base 2 depending on the value of
* Exp Bus config registers:
*
* Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
* and The expansion bus to IXP425_EXP_BUS_BASE2
*/
#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000)
#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT
#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
#define IXP425_FLASH_WRITABLE (0x2)
#define IXP425_FLASH_DEFAULT (0xbcd23c40)
#define IXP425_FLASH_WRITE (0xbcd23c42)
#define IXP425_EXP_CS0_OFFSET 0x00
#define IXP425_EXP_CS1_OFFSET 0x04
#define IXP425_EXP_CS2_OFFSET 0x08
#define IXP425_EXP_CS3_OFFSET 0x0C
#define IXP425_EXP_CS4_OFFSET 0x10
#define IXP425_EXP_CS5_OFFSET 0x14
#define IXP425_EXP_CS6_OFFSET 0x18
#define IXP425_EXP_CS7_OFFSET 0x1C
#define IXP425_EXP_CFG0_OFFSET 0x20
#define IXP425_EXP_CFG1_OFFSET 0x24
#define IXP425_EXP_CFG2_OFFSET 0x28
#define IXP425_EXP_CFG3_OFFSET 0x2C
/*
* Expansion Bus Controller registers.
*/
#ifndef __ASSEMBLY__
#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x)))
#else
#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
#endif
#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
/*
* SDRAM Controller registers.
*/
#define IXP425_SDR_CONFIG_OFFSET 0x00
#define IXP425_SDR_REFRESH_OFFSET 0x04
#define IXP425_SDR_IR_OFFSET 0x08
#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
/*
* UART registers
*/
#define IXP425_UART1 0
#define IXP425_UART2 0x1000
#define IXP425_UART_RBR_OFFSET 0x00
#define IXP425_UART_THR_OFFSET 0x00
#define IXP425_UART_DLL_OFFSET 0x00
#define IXP425_UART_IER_OFFSET 0x04
#define IXP425_UART_DLH_OFFSET 0x04
#define IXP425_UART_IIR_OFFSET 0x08
#define IXP425_UART_FCR_OFFSET 0x00
#define IXP425_UART_LCR_OFFSET 0x0c
#define IXP425_UART_MCR_OFFSET 0x10
#define IXP425_UART_LSR_OFFSET 0x14
#define IXP425_UART_MSR_OFFSET 0x18
#define IXP425_UART_SPR_OFFSET 0x1c
#define IXP425_UART_ISR_OFFSET 0x20
#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
#define IIR_TOD (1 << 3) /* Time Out Detected */
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1 (0)
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
#define LCR_SB (1 << 6) /* Set Break */
#define LCR_STKYP (1 << 5) /* Sticky Parity */
#define LCR_EPS (1 << 4) /* Even Parity Select */
#define LCR_PEN (1 << 3) /* Parity Enable */
#define LCR_STB (1 << 2) /* Stop Bit */
#define LCR_WLS1 (1 << 1) /* Word Length Select */
#define LCR_WLS0 (1 << 0) /* Word Length Select */
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
#define LSR_BI (1 << 4) /* Break Interrupt */
#define LSR_FE (1 << 3) /* Framing Error */
#define LSR_PE (1 << 2) /* Parity Error */
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
#define MCR_LOOP (1 << 4) */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
#define MCR_DTR (1 << 0) /* Data Terminal Ready */
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?