📄 platform.h
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; FLASH memory maximum 8MB
; |------------------------------| 0x04000000
; | Base IO bank (0x03ff0000) |
; |------------------------------| 0x03FF0000
; |------------------------------| 0x03E00000
; | External I/O bank 2 |
; |------------------------------| 0x03A00000
; | External I/O bank 1 |
; |------------------------------| 0x03600000
; | External I/O bank 0 |
; |------------------------------| 0x03200000
; | FLASH |
; |------------------------------| 0x02800000
; | SPACE |
; | |
; |------------------------------| 0x01480000
; | SPACE |
; |------------------------------| 0x01400000
; | SPACE |
; | |
; |------------------------------| 0x01080000
; | SDRAM BANK 1 |
; |------------------------------| 0x00880000
; | SDRAM BANK 0 |
; |------------------------------| 0x00080000
; | SRAM |
; |------------------------------| 0x00000000
;
; Figure 1. Memmry Map With SRAM
;
; B. remappped memory map for new board without
; SRAM, SDRAM maximun 32MB, FLASH maximum 8MB
; |------------------------------| 0x04000000
; | Base IO bank (0x03ff0000) |
; |------------------------------| 0x03FF0000
; |------------------------------| 0x03E00000
; | External I/O bank 2 |
; |------------------------------| 0x03A00000
; | External I/O bank 1 |
; |------------------------------| 0x03600000
; | External I/O bank 0 |
; |------------------------------| 0x03200000
; | FLASH |
; |------------------------------| 0x02800000
; | SPACE |
; | |
; |------------------------------| 0x01480000
; | SPACE |
; |------------------------------| 0x01400000
; | SPACE |
; | |
; |------------------------------| 0x01000000
; | SDRAM BANK 1 |
; |------------------------------| 0x00800000
; | SDRAM BANK 0 |
; |------------------------------| 0x00000000
; Figure 2. Memory Map Without SRAM
*********************************************/
/* clock indices */
#define SYSTEN_BUS_CLOCK_125 0x0
#define SYSTEN_BUS_CLOCK_100 0x1
#define SYSTEN_BUS_CLOCK_625 0x2
#define SYSTEN_BUS_CLOCK_050 0x3
#define SYSTEN_BUS_CLOCK_417 0x4
#define SYSTEN_BUS_CLOCK_333 0x5
#define SYSTEN_BUS_CLOCK_313 0x6
#define SYSTEN_BUS_CLOCK_025 0x7
/* cpu parameters */
#define MODE_USR 0x10
#define MODE_FIQ 0x11
#define MODE_IRQ 0x12
#define MODE_SVC 0x13
#define MODE_ABT 0x17
#define MODE_UNDEF 0x1B
#define MODE_SYS 0x1F /* available on ARM Arch 4 and later */
#define I_BIT 0x80 /* when I bit is set, IRQ is disabled */
#define F_BIT 0x40 /* when F bit is set, FIQ is disabled */
/* other parameters to set up FLASH/ROM/SRAM configuration registers */
#define ROM_TIME_MULTIPLER_0 0x0
#define ROM_TIME_MULTIPLER_1 (0x1 << 28)
#define ROM_TIME_MULTIPLER_2 (0x2 << 28)
#define ROM_TIME_MULTIPLER_3 (0x3 << 28)
#define ROM_BANK_ACCTM2 0x0
#define ROM_BANK_ACCTM3 (0x1 << 4)
#define ROM_BANK_ACCTM4 (0x2 << 4)
#define ROM_BANK_ACCTM5 (0x3 << 4)
#define ROM_BANK_ACCTM6 (0x4 << 4)
#define ROM_BANK_ACCTM7 (0x5 << 4)
#define ROM_BANK_ACCTM8 (0x6 << 4)
#define ROM_BANK_ACCTM9 (0x7 << 4)
#define ROM_BANK_ACCTM3_1 0x0
#define ROM_BANK_ACCTM5_1 (0x1 << 4)
#define ROM_BANK_ACCTM7_1 (0x2 << 4)
#define ROM_BANK_ACCTM9_1 (0x3 << 4)
#define ROM_BANK_ACCTM11_1 (0x4 << 4)
#define ROM_BANK_ACCTM13_1 (0x5 << 4)
#define ROM_BANK_ACCTM15_1 (0x6 << 4)
#define ROM_BANK_ACCTM17_1 (0x7 << 4)
#define ROM_BANK_PACTM2 0x0
#define ROM_BANK_PACTM3 (0x1 << 2)
#define ROM_BANK_PACTM4 (0x2 << 2)
#define ROM_BANK_PACTM5 (0x3 << 2)
#define ROM_BANK_PACTM3_1 0x0
#define ROM_BANK_PACTM5_1 (0x1 << 2)
#define ROM_BANK_PACTM7_1 (0x2 << 2)
#define ROM_BANK_PACTM9_1 (0x3 << 2)
#define ROM_BANK_PMOD0 0x0
#define ROM_BANK_PMOD1 0x1
#define ROM_BANK_PMOD2 0x2
#define ROM_BANK_PMOD3 0x3
/* SDRAM banks */
#define BOOT_START 0x00400000 /*linux bootloader C code start address*/
#define DIAG_START 0x00080000 /*diagnostic program C code start address*/
#define LEVEL1TABLE 0x00040000 /*where the MMU table is stored */
#define SDRAM_NOP_COMD 0x30000
#define SDRAM_PRECHARGE_CMD 0x10000
#if defined(CONFIG_ARCH_KS8695L) || defined(CONFIG_ARCH_KS8695V) || defined(CONFIG_ARCH_KS8695PM)
#define SDRAM_REFRESH_TIMER 360
#else
#define SDRAM_REFRESH_TIMER 390
#endif
#define SDRAM_MODE_COMD 0x20033
#define SDRAM_RASCAS 0x0000000A
#ifdef USE_SRAM
#define ROM_GENERAL_SETTING 0x0000000D
#else
#if defined(CONFIG_ARCH_KS8695) || defined(CONFIG_ARCH_KS8695X)
#define ROM_GENERAL_SETTING 0x00000001 /*0x1 for 8 bit flash, 2 for 16 bit and 3 for 32 bit*/
#elif defined( CONFIG_ARCH_KS8695P )
#define ROM_GENERAL_SETTING (ROM_TIME_MULTIPLER_1|0x00000001)
#elif defined(CONFIG_ARCH_KS8695PM) || defined(CONFIG_ARCH_KS8695MB)
#define ROM_GENERAL_SETTING 0x1003000F /*0x1 for 8 bit flash, 2 for 16 bit and 3 for 32 bit*/
#elif defined( CONFIG_ARCH_KS8695V )
#if defined( CONFIG_KS8695V1 )
#define ROM_GENERAL_SETTING (ROM_TIME_MULTIPLER_1|0x00030003)
#else
#define ROM_GENERAL_SETTING (ROM_TIME_MULTIPLER_1|0x00030002)
#endif
#elif defined(CONFIG_ARCH_KS8695L)
#define ROM_GENERAL_SETTING 0x10000002
#endif
#endif
#if !defined(CONFIG_ARCH_KS8695L)
#define FLASH_BANK_SIZE 0x00800000
#else
#define FLASH_BANK_SIZE 0x00400000
#endif
#if defined(CONFIG_ARCH_KS8695PM) || defined (CONFIG_ARCH_KS8695MB)
#define FLASH_BANK_SIZE_1 0x00800000
#else
#define FLASH_BANK_SIZE_1 0x00000000
#endif
#define SRAM_BANK_SIZE 0x00080000
/* memory configuration */
#define FLASH_BANK 0
#define REMAPPED_FLASH_BANK PHYS_FLASH_1
#ifdef USE_SRAM
#define SRAM_BANK FLASH_BANK_SIZE
#define REMAPPED_SRAM_BANK 0x00000000
#define SDRAM_BANK_0 (SRAM_BANK + SRAM_BANK_SIZE)
#define REMAPPED_SDRAM_BANK_0 (REMAPPED_SRAM_BANK + SRAM_BANK_SIZE)
#else
#define SDRAM_BANK_0 FLASH_BANK_SIZE
#define REMAPPED_SDRAM_BANK_0 PHYS_SDRAM_1
#endif
#define FLASH_BANK0_SIZE 0x00800000
#define REMAPPED_FLASH_BANK_1 (REMAPPED_FLASH_BANK + FLASH_BANK0_SIZE)
#define SDRAM_BANK0_SIZE PHYS_SDRAM_1_SIZE
#define SDRAM_BANK1_SIZE PHYS_SDRAM_2_SIZE
#define SDRAM_BANK_1 (SDRAM_BANK_0 + SDRAM_BANK0_SIZE)
#define SDRAM_BANK_END (SDRAM_BANK_1 + SDRAM_BANK1_SIZE)
#define REMAPPED_SDRAM_BANK_1 (REMAPPED_SDRAM_BANK_0 + SDRAM_BANK0_SIZE)
#define REMAPPED_SDRAM_BANK_END (REMAPPED_SDRAM_BANK_1 + SDRAM_BANK1_SIZE)
#define SDRAM_BANK_COLAB8 0x0
#define SDRAM_BANK_COLAB9 (0x1 << 8)
#define SDRAM_BANK_COLAB10 (0x2 << 8)
#define SDRAM_BANK_COLAB11 (0x3 << 8)
#define SDRAM_UNM_BANKS2 0x0
#define SDRAM_UNM_BANKS4 (0x1 << 3)
#define SDRAM_BANKS_DBW0 0x0
#define SDRAM_BANKS_DBW8 (0x1 << 1)
#define SDRAM_BANKS_DBW16 (0x2 << 1)
#define SDRAM_BANKS_DBW32 (0x3 << 1)
/* External I/O banks defintions */
#ifdef CONFIG_ARCH_KS8695MB
#define EXT_IO_BANK_SIZE 0x00100000
#define EXT_IO_BANK_0 0x03C00000
#elif defined( CONFIG_ARCH_KS8695PM )
#define EXT_IO_BANK_SIZE 0x00400000
#define EXT_IO_BANK_0 0x03200000
#else
#define EXT_IO_BANK_SIZE 0x00200000
#define EXT_IO_BANK_0 0x03400000
#endif
#define EXT_IO_BANK_1 (EXT_IO_BANK_0 + EXT_IO_BANK_SIZE)
#define EXT_IO_BANK_2 (EXT_IO_BANK_1 + EXT_IO_BANK_SIZE)
#define EXT_IOBANK_CLOCK0 0x0
#define EXT_IOBANK_CLOCK1 0x1
#define EXT_IOBANK_CLOCK2 0x2
#define EXT_IOBANK_CLOCK3 0x3
#define EXT_IOBANK_CLOCK4 0x4
#define EXT_IOBANK_CLOCK5 0x5
#define EXT_IOBANK_CLOCK6 0x6
#define EXT_IOBANK_CLOCK7 0x7
/* --- System memory locations */
#ifdef ROM_RAM_REMAP
#define RAM_LIMIT REMAPPED_SDRAM_BANK_END
#else
#define RAM_LIMIT SDRAM_BANK_END
#endif
#define ABT_STACK RAM_LIMIT
#define UNDEF_STACK ABT_STACK - 1024
#define SVC_STACK UNDEF_STACK - 1024
#define IRQ_STACK SVC_STACK - 2048
#define FIQ_STACK IRQ_STACK - 4096
#define SYS_STACK FIQ_STACK - 4096
#define USR_STACK SYS_STACK - 4096
#define RAM_LIMIT_TMP SDRAM_BANK_END - 2048
#define FLASH_ROM_START REMAPPED_FLASH_BANK
#define SDRAM_START SDRAM_BANK_0
#if !defined(CONFIG_ARCH_KS8695L) && !defined( CONFIG_ARCH_KS8695V )
#if defined( CONFIG_KS8695M )
#define ROM_BANK_ACCESSTIME ROM_BANK_ACCTM11_1
#elif defined( CONFIG_ARCH_KS8695P )
#define ROM_BANK_ACCESSTIME ROM_BANK_ACCTM9_1
#else
#define ROM_BANK_ACCESSTIME ROM_BANK_ACCTM9
#endif
#define SDRAM_BANKS_WIDTH SDRAM_BANKS_DBW32
#define REM_FLASH_REG1 0
#else
#if defined( CONFIG_ARCH_KS8695V )
#define ROM_BANK_ACCESSTIME ROM_BANK_ACCTM11_1
#else
#define ROM_BANK_ACCESSTIME ROM_BANK_ACCTM9
#endif
#if defined( CONFIG_KS8695V1 )
#define SDRAM_BANKS_WIDTH SDRAM_BANKS_DBW32
#else
#define SDRAM_BANKS_WIDTH SDRAM_BANKS_DBW16
#endif
#define REM_FLASH_REG1 0
#endif
/*
* calculating all the memory bank configuration register value which used to take me a lot of
* my time and often ends up with errors and now it will be done automatically.
*/
#define FLASH_REG_VAL( start, size ) \
((((start)+(size)-1)>>16)<<22)|(((start)>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCESSTIME
#define SDRAM_REG_VAL( start, size ) \
((((start)+(size)-1)>>16)<<22)|(((start)>>16)<<12)|SDRAM_UNM_BANKS4|SDRAM_BANKS_WIDTH
#define TMP_FLASH_REG0 FLASH_REG_VAL( FLASH_BANK, FLASH_BANK0_SIZE )
#define REM_FLASH_REG0 FLASH_REG_VAL( REMAPPED_FLASH_BANK, FLASH_BANK0_SIZE )
#define TMP_SDRAM_REG0 SDRAM_REG_VAL( SDRAM_BANK_0, SDRAM_BANK0_SIZE )
#define REM_SDRAM_REG0 SDRAM_REG_VAL( REMAPPED_SDRAM_BANK_0, SDRAM_BANK0_SIZE )
#ifdef USE_SRAM
#define SRAM_REG (((SRAM_BANK+SRAM_BANK_SIZE-1)>>16)<<22)|((SRAM_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM5
#define REM_SRAM_REG (((REMAPPED_SRAM_BANK+SRAM_BANK_SIZE-1)>>16)<<22)|((REMAPPED_SRAM_BANK>>16)<<12)|ROM_BANK_PMOD0|ROM_BANK_ACCTM5
#endif
#if SDRAM_BANK1_SIZE == 0
#define TMP_SDRAM_REG1 0
#define SDRAM_REG1 0
#define REM_SDRAM_REG1 0
#else
#define TMP_SDRAM_REG1 SDRAM_REG_VAL( SDRAM_BANK_1, SDRAM_BANK1_SIZE )
#define REM_SDRAM_REG1 SDRAM_REG_VAL( REMAPPED_SDRAM_BANK_1, SDRAM_BANK1_SIZE )
#endif
#if defined(CONFIG_ARCH_KS8695PM) || defined(CONFIG_ARCH_KS8695MB)
#ifdef REM_FLASH_REG1
#undef REM_FLASH_REG1
#endif
#define REM_FLASH_REG1 FLASH_REG_VAL( REMAPPED_FLASH_BANK_1, FLASH_BANK1_SIZE )
#endif
#define EXTIO_REG0 (((EXT_IO_BANK_0+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_0>>16)<<12)|(EXT_IOBANK_CLOCK6<<9)
#define EXTIO_REG1 (((EXT_IO_BANK_1+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_1>>16)<<12)|(EXT_IOBANK_CLOCK6<<9)
#define EXTIO_REG2 (((EXT_IO_BANK_2+EXT_IO_BANK_SIZE-1)>>16)<<22)|((EXT_IO_BANK_2>>16)<<12)|(EXT_IOBANK_CLOCK6<<9)
#endif
/* END */
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