skdrv2nd.h

适合KS8695X

};


/* definition of flags in descriptor control field */
#define	RX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
#define	RX_CTRL_STF		UINT32_C(0x40000000)
#define	RX_CTRL_EOF		UINT32_C(0x20000000)
#define	RX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
#define	RX_CTRL_EOF_IRQ		UINT32_C(0x08000000)
#define RX_CTRL_DEV_NULL	UINT32_C(0x04000000)
#define RX_CTRL_STAT_VALID	UINT32_C(0x02000000)
#define RX_CTRL_TIME_VALID	UINT32_C(0x01000000)
#define RX_CTRL_CHECK_DEFAULT	UINT32_C(0x00550000)
#define RX_CTRL_CHECK_CSUM	UINT32_C(0x00560000)
#define	RX_CTRL_LEN_MASK	UINT32_C(0x0000FFFF)

#define	TX_CTRL_OWN_BMU 	UINT32_C(0x80000000)
#define	TX_CTRL_STF		UINT32_C(0x40000000)
#define	TX_CTRL_EOF		UINT32_C(0x20000000)
#define	TX_CTRL_EOB_IRQ		UINT32_C(0x10000000)
#define	TX_CTRL_EOF_IRQ		UINT32_C(0x08000000)
#define TX_CTRL_ST_FWD		UINT32_C(0x04000000)
#define TX_CTRL_DISAB_CRC	UINT32_C(0x02000000)
#define TX_CTRL_SOFTWARE	UINT32_C(0x01000000)
#define TX_CTRL_CHECK_DEFAULT	UINT32_C(0x00550000)
#define TX_CTRL_CHECK_CSUM	UINT32_C(0x00560000)
#define	TX_CTRL_LEN_MASK	UINT32_C(0x0000FFFF)


/* The offsets of registers in the TX and RX queue control io area ***********/

#define RX_Q_BUF_CTRL_CNT	0x00
#define RX_Q_NEXT_DESCR_LOW	0x04
#define RX_Q_BUF_ADDR_LOW	0x08
#define RX_Q_BUF_ADDR_HIGH	0x0c
#define RX_Q_FRAME_STAT		0x10
#define RX_Q_TIME_STAMP		0x14
#define RX_Q_CSUM_1_2		0x18
#define RX_Q_CSUM_START_1_2	0x1c
#define RX_Q_CUR_DESCR_LOW	0x20
#define RX_Q_DESCR_HIGH		0x24
#define RX_Q_CUR_ADDR_LOW	0x28
#define RX_Q_CUR_ADDR_HIGH	0x2c
#define RX_Q_CUR_BYTE_CNT	0x30
#define RX_Q_CTRL		0x34
#define RX_Q_FLAG		0x38
#define RX_Q_TEST1		0x3c
#define RX_Q_TEST2		0x40
#define RX_Q_TEST3		0x44

#define TX_Q_BUF_CTRL_CNT	0x00
#define TX_Q_NEXT_DESCR_LOW	0x04
#define TX_Q_BUF_ADDR_LOW	0x08
#define TX_Q_BUF_ADDR_HIGH	0x0c
#define TX_Q_FRAME_STAT		0x10
#define TX_Q_CSUM_START		0x14
#define TX_Q_CSUM_START_POS	0x18
#define TX_Q_RESERVED		0x1c
#define TX_Q_CUR_DESCR_LOW	0x20
#define TX_Q_DESCR_HIGH		0x24
#define TX_Q_CUR_ADDR_LOW	0x28
#define TX_Q_CUR_ADDR_HIGH	0x2c
#define TX_Q_CUR_BYTE_CNT	0x30
#define TX_Q_CTRL		0x34
#define TX_Q_FLAG		0x38
#define TX_Q_TEST1		0x3c
#define TX_Q_TEST2		0x40
#define TX_Q_TEST3		0x44

/* definition of flags in the queue control field */
#define RX_Q_CTRL_POLL_ON	0x00000080
#define RX_Q_CTRL_POLL_OFF	0x00000040
#define RX_Q_CTRL_STOP		0x00000020
#define RX_Q_CTRL_START		0x00000010
#define RX_Q_CTRL_CLR_I_PAR	0x00000008
#define RX_Q_CTRL_CLR_I_EOB	0x00000004
#define RX_Q_CTRL_CLR_I_EOF	0x00000002
#define RX_Q_CTRL_CLR_I_ERR	0x00000001

#define TX_Q_CTRL_POLL_ON	0x00000080
#define TX_Q_CTRL_POLL_OFF	0x00000040
#define TX_Q_CTRL_STOP		0x00000020
#define TX_Q_CTRL_START		0x00000010
#define TX_Q_CTRL_CLR_I_EOB	0x00000004
#define TX_Q_CTRL_CLR_I_EOF	0x00000002
#define TX_Q_CTRL_CLR_I_ERR	0x00000001


/* Interrupt bits in the interrupts source register **************************/
#define IRQ_HW_ERROR		0x80000000
#define IRQ_RESERVED		0x40000000
#define IRQ_PKT_TOUT_RX1	0x20000000
#define IRQ_PKT_TOUT_RX2	0x10000000
#define IRQ_PKT_TOUT_TX1	0x08000000
#define IRQ_PKT_TOUT_TX2	0x04000000
#define IRQ_I2C_READY		0x02000000
#define IRQ_SW			0x01000000
#define IRQ_EXTERNAL_REG	0x00800000
#define IRQ_TIMER		0x00400000
#define IRQ_MAC1		0x00200000
#define IRQ_LINK_SYNC_C_M1	0x00100000
#define IRQ_MAC2		0x00080000
#define IRQ_LINK_SYNC_C_M2	0x00040000
#define IRQ_EOB_RX1		0x00020000
#define IRQ_EOF_RX1		0x00010000
#define IRQ_CHK_RX1		0x00008000
#define IRQ_EOB_RX2		0x00004000
#define IRQ_EOF_RX2		0x00002000
#define IRQ_CHK_RX2		0x00001000
#define IRQ_EOB_SY_TX1		0x00000800
#define IRQ_EOF_SY_TX1		0x00000400
#define IRQ_CHK_SY_TX1		0x00000200
#define IRQ_EOB_AS_TX1		0x00000100
#define IRQ_EOF_AS_TX1		0x00000080
#define IRQ_CHK_AS_TX1		0x00000040
#define IRQ_EOB_SY_TX2		0x00000020
#define IRQ_EOF_SY_TX2		0x00000010
#define IRQ_CHK_SY_TX2		0x00000008
#define IRQ_EOB_AS_TX2		0x00000004
#define IRQ_EOF_AS_TX2		0x00000002
#define IRQ_CHK_AS_TX2		0x00000001

#define DRIVER_IRQS	(IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \
			IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \
			IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2)

#define SPECIAL_IRQS	(IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
			IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
			IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
			IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \
			IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \
			IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
			IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
			IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)

#define IRQ_MASK	(IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \
			IRQ_EOB_RX2 | IRQ_EOF_RX2 | \
			IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \
			IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \
			IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \
			IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \
			IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \
			IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \
			IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \
			IRQ_MAC1 | \
			IRQ_MAC2 | \
			IRQ_CHK_RX1 | IRQ_CHK_RX2 | \
			IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \
			IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2)

#define IRQ_HWE_MASK	0x00000FFF /* enable all HW irqs */

typedef struct s_DevNet DEV_NET;

struct s_DevNet {
	int             PortNr;
	int             NetNr;
	int             Mtu;
	int             Up;
	SK_AC   *pAC;
};

typedef struct s_TxPort		TX_PORT;

struct s_TxPort {
	/* the transmit descriptor rings */
	caddr_t		pTxDescrRing;	/* descriptor area memory */
	SK_U64		VTxDescrRing;	/* descr. area bus virt. addr. */
	TXD		*pTxdRingHead;	/* Head of Tx rings */
	TXD		*pTxdRingTail;	/* Tail of Tx rings */
	TXD		*pTxdRingPrev;	/* descriptor sent previously */
	int		TxdRingFree;	/* # of free entrys */
#if 0
	spinlock_t	TxDesRingLock;	/* serialize descriptor accesses */
#endif
	caddr_t		HwAddr;		/* bmu registers address */
	int		PortIndex;	/* index number of port (0 or 1) */
};

typedef struct s_RxPort		RX_PORT;

struct s_RxPort {
	/* the receive descriptor rings */
	caddr_t		pRxDescrRing;	/* descriptor area memory */
	SK_U64		VRxDescrRing;   /* descr. area bus virt. addr. */
	RXD		*pRxdRingHead;	/* Head of Rx rings */
	RXD		*pRxdRingTail;	/* Tail of Rx rings */
	RXD		*pRxdRingPrev;	/* descriptor given to BMU previously */
	int		RxdRingFree;	/* # of free entrys */
#if 0
	spinlock_t	RxDesRingLock;	/* serialize descriptor accesses */
#endif
	int		RxFillLimit;	/* limit for buffers in ring */
	caddr_t		HwAddr;		/* bmu registers address */
	int		PortIndex;	/* index number of port (0 or 1) */
};

typedef struct s_PerStrm	PER_STRM;

#define SK_ALLOC_IRQ	0x00000001

/****************************************************************************
 * Per board structure / Adapter Context structure:
 *	Allocated within attach(9e) and freed within detach(9e).
 *	Contains all 'per device' necessary handles, flags, locks etc.:
 */
struct s_AC  {
	SK_GEINIT	GIni;		/* GE init struct */
	SK_PNMI		Pnmi;		/* PNMI data struct */
	SK_VPD		vpd;		/* vpd data struct */
	SK_QUEUE	Event;		/* Event queue */
	SK_HWT		Hwt;		/* Hardware Timer control struct */
	SK_TIMCTRL	Tim;		/* Software Timer control struct */
	SK_I2C		I2c;		/* I2C relevant data structure */
	SK_ADDR		Addr;		/* for Address module */
	SK_CSUM		Csum;		/* for checksum module */
	SK_RLMT		Rlmt;		/* for rlmt module */
#if 0
	spinlock_t	SlowPathLock;	/* Normal IRQ lock */
#endif
	SK_PNMI_STRUCT_DATA PnmiStruct;	/* structure to get all Pnmi-Data */
	int			RlmtMode;	/* link check mode to set */
	int			RlmtNets;	/* Number of nets */

	SK_IOC		IoBase;		/* register set of adapter */
	int		BoardLevel;	/* level of active hw init (0-2) */
	char		DeviceStr[80];	/* adapter string from vpd */
	SK_U32		AllocFlag;	/* flag allocation of resources */
#if 0
	struct pci_dev	*PciDev;	/* for access to pci config space */
	SK_U32		PciDevId;	/* pci device id */
#else
	int		PciDev;
#endif
	struct SK_NET_DEVICE	*dev[2];	/* pointer to device struct */
	char		Name[30];	/* driver name */
	struct SK_NET_DEVICE	*Next;		/* link all devices (for clearing) */
	int		RxBufSize;	/* length of receive buffers */
#if 0
	struct net_device_stats stats;	/* linux 'netstat -i' statistics */
#endif
	int		Index;		/* internal board index number */

	/* adapter RAM sizes for queues of active port */
	int		RxQueueSize;	/* memory used for receive queue */
	int		TxSQueueSize;	/* memory used for sync. tx queue */
	int		TxAQueueSize;	/* memory used for async. tx queue */

	int		PromiscCount;	/* promiscuous mode counter  */
	int		AllMultiCount;  /* allmulticast mode counter */
	int		MulticCount;	/* number of different MC    */
					/*  addresses for this board */
					/*  (may be more than HW can)*/

	int		HWRevision;	/* Hardware revision */
	int		ActivePort;	/* the active XMAC port */
	int		MaxPorts;		/* number of activated ports */
	int		TxDescrPerRing;	/* # of descriptors per tx ring */
	int		RxDescrPerRing;	/* # of descriptors per rx ring */

	caddr_t		pDescrMem;	/* Pointer to the descriptor area */
	dma_addr_t	pDescrMemDMA;	/* PCI DMA address of area */

	/* the port structures with descriptor rings */
	TX_PORT		TxPort[SK_MAX_MACS][2];
	RX_PORT		RxPort[SK_MAX_MACS];

	unsigned int	CsOfs1;		/* for checksum calculation */
	unsigned int	CsOfs2;		/* for checksum calculation */
	SK_U32		CsOfs;		/* for checksum calculation */

	SK_BOOL		CheckQueue;	/* check event queue soon */

	/* Only for tests */
	int		PortUp;
	int		PortDown;

};

#endif /* __INC_SKDRV2ND_H */