skgehw.h

适合KS8695X

/*	B2_I2C_IRQ	32 bit	I2C HW IRQ Register */
								/* Bit 31.. 1	reserved */
#define I2C_CLR_IRQ		BIT_0	/* Clear I2C IRQ */

/*	B2_I2C_SW	32 bit (8 bit access)	I2C HW SW Port Register */
								/* Bit  7.. 3:	reserved */
#define I2C_DATA_DIR	BIT_2S		/* direction of I2C_DATA */
#define I2C_DATA		BIT_1S		/* I2C Data Port	*/
#define I2C_CLK			BIT_0S		/* I2C Clock Port	*/

/*
 * I2C Address
 */
#define I2C_SENS_ADDR	LM80_ADDR	/* I2C Sensor Address, (Volt and Temp)*/


/*	B2_BSC_CTRL	 8 bit	Blink Source Counter Control */
							/* Bit  7.. 2:	reserved */
#define BSC_START	BIT_1S		/* Start Blink Source Counter */
#define BSC_STOP	BIT_0S		/* Stop  Blink Source Counter */

/*	B2_BSC_STAT	 8 bit	Blink Source Counter Status */
							/* Bit  7.. 1:	reserved */
#define BSC_SRC		BIT_0S		/* Blink Source, 0=Off / 1=On */

/*	B2_BSC_TST	16 bit	Blink Source Counter Test Reg */
#define BSC_T_ON	BIT_2S		/* Test mode on */
#define BSC_T_OFF	BIT_1S		/* Test mode off */
#define BSC_T_STEP	BIT_0S		/* Test step */


/*	B3_RAM_ADDR	32 bit	RAM Address, to read or write */
					/* Bit 31..19:	reserved */
#define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */

/* RAM Interface Registers */
/*	B3_RI_CTRL	16 bit	RAM Iface Control Register */
								/* Bit 15..10:	reserved */
#define RI_CLR_RD_PERR	BIT_9S	/* Clear IRQ RAM Read Parity Err */
#define RI_CLR_WR_PERR	BIT_8S	/* Clear IRQ RAM Write Parity Err*/
								/* Bit	7.. 2:	reserved */
#define RI_RST_CLR		BIT_1S	/* Clear RAM Interface Reset */
#define RI_RST_SET		BIT_0S	/* Set   RAM Interface Reset */

/*	B3_RI_TEST	 8 bit	RAM Iface Test Register */
								/* Bit 15.. 4:	reserved */
#define RI_T_EV			BIT_3S	/* Timeout Event occured */
#define RI_T_ON			BIT_2S	/* Timeout Timer Test On */
#define RI_T_OFF		BIT_1S	/* Timeout Timer Test Off */
#define RI_T_STEP		BIT_0S	/* Timeout Timer Step */

/* MAC Arbiter Registers */
/*	B3_MA_TO_CTRL	16 bit	MAC Arbiter Timeout Ctrl Reg */
								/* Bit 15.. 4:	reserved */
#define MA_FOE_ON		BIT_3S	/* XMAC Fast Output Enable ON */
#define MA_FOE_OFF		BIT_2S	/* XMAC Fast Output Enable OFF */
#define MA_RST_CLR		BIT_1S	/* Clear MAC Arbiter Reset */
#define MA_RST_SET		BIT_0S	/* Set   MAC Arbiter Reset */

/*	B3_MA_RC_CTRL	16 bit	MAC Arbiter Recovery Ctrl Reg */
								/* Bit 15.. 8:	reserved */
#define MA_ENA_REC_TX2	BIT_7S	/* Enable  Recovery Timer TX2 */
#define MA_DIS_REC_TX2	BIT_6S	/* Disable Recovery Timer TX2 */
#define MA_ENA_REC_TX1	BIT_5S	/* Enable  Recovery Timer TX1 */
#define MA_DIS_REC_TX1	BIT_4S	/* Disable Recovery Timer TX1 */
#define MA_ENA_REC_RX2	BIT_3S	/* Enable  Recovery Timer RX2 */
#define MA_DIS_REC_RX2	BIT_2S	/* Disable Recovery Timer RX2 */
#define MA_ENA_REC_RX1	BIT_1S	/* Enable  Recovery Timer RX1 */
#define MA_DIS_REC_RX1	BIT_0S	/* Disable Recovery Timer RX1 */

/* Packet Arbiter Registers */
/*	B3_PA_CTRL	16 bit	Packet Arbiter Ctrl Register */
								/* Bit 15..14:	reserved */
#define PA_CLR_TO_TX2	BIT_13S	/* Clear IRQ Packet Timeout TX2 */
#define PA_CLR_TO_TX1	BIT_12S	/* Clear IRQ Packet Timeout TX1 */
#define PA_CLR_TO_RX2	BIT_11S	/* Clear IRQ Packet Timeout RX2 */
#define PA_CLR_TO_RX1	BIT_10S	/* Clear IRQ Packet Timeout RX1 */
#define PA_ENA_TO_TX2	BIT_9S	/* Enable  Timeout Timer TX2 */
#define PA_DIS_TO_TX2	BIT_8S	/* Disable Timeout Timer TX2 */
#define PA_ENA_TO_TX1	BIT_7S	/* Enable  Timeout Timer TX1 */
#define PA_DIS_TO_TX1	BIT_6S	/* Disable Timeout Timer TX1 */
#define PA_ENA_TO_RX2	BIT_5S	/* Enable  Timeout Timer RX2 */
#define PA_DIS_TO_RX2	BIT_4S	/* Disable Timeout Timer RX2 */
#define PA_ENA_TO_RX1	BIT_3S	/* Enable  Timeout Timer RX1 */
#define PA_DIS_TO_RX1	BIT_2S	/* Disable Timeout Timer RX1 */
#define PA_RST_CLR		BIT_1S	/* Clear MAC Arbiter Reset */
#define PA_RST_SET		BIT_0S	/* Set   MAC Arbiter Reset */

#define PA_ENA_TO_ALL	(PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
						PA_ENA_TO_TX1 | PA_ENA_TO_TX2)

/* Rx/Tx Path related Arbiter Test Registers */
/*	B3_MA_TO_TEST	16 bit	MAC Arbiter Timeout Test Reg */
/*	B3_MA_RC_TEST	16 bit	MAC Arbiter Recovery Test Reg */
/*	B3_PA_TEST	16 bit	Packet Arbiter Test Register */
/*			Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
#define TX2_T_EV	BIT_15S		/* TX2 Timeout/Recv Event occured */
#define TX2_T_ON	BIT_14S		/* TX2 Timeout/Recv Timer Test On */
#define TX2_T_OFF	BIT_13S		/* TX2 Timeout/Recv Timer Tst Off */
#define TX2_T_STEP	BIT_12S		/* TX2 Timeout/Recv Timer Step */
#define TX1_T_EV	BIT_11S		/* TX1 Timeout/Recv Event occured */
#define TX1_T_ON	BIT_10S		/* TX1 Timeout/Recv Timer Test On */
#define TX1_T_OFF	BIT_9S		/* TX1 Timeout/Recv Timer Tst Off */
#define TX1_T_STEP	BIT_8S		/* TX1 Timeout/Recv Timer Step */
#define RX2_T_EV	BIT_7S		/* RX2 Timeout/Recv Event occured */
#define RX2_T_ON	BIT_6S		/* RX2 Timeout/Recv Timer Test On */
#define RX2_T_OFF	BIT_5S		/* RX2 Timeout/Recv Timer Tst Off */
#define RX2_T_STEP	BIT_4S		/* RX2 Timeout/Recv Timer Step */
#define RX1_T_EV	BIT_3S		/* RX1 Timeout/Recv Event occured */
#define RX1_T_ON	BIT_2S		/* RX1 Timeout/Recv Timer Test On */
#define RX1_T_OFF	BIT_1S		/* RX1 Timeout/Recv Timer Tst Off */
#define RX1_T_STEP	BIT_0S		/* RX1 Timeout/Recv Timer Step */


/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
/*	TXA_ITI_INI	32 bit	Tx Arb Interval Timer Init Val */
/*	TXA_ITI_VAL	32 bit	Tx Arb Interval Timer Value */
/*	TXA_LIM_INI	32 bit	Tx Arb Limit Counter Init Val */
/*	TXA_LIM_VAL	32 bit	Tx Arb Limit Counter Value */
								/* Bit 31..24:	reserved */
#define TXA_MAX_VAL	0x00ffffffL	/* Bit 23.. 0:	Max TXA Timer/Cnt Val */

/*	TXA_CTRL	 8 bit	Tx Arbiter Control Register */
#define TXA_ENA_FSYNC	BIT_7S	/* Enable  force of sync Tx queue */
#define TXA_DIS_FSYNC	BIT_6S	/* Disable force of sync Tx queue */
#define TXA_ENA_ALLOC	BIT_5S	/* Enable  alloc of free bandwidth */
#define TXA_DIS_ALLOC	BIT_4S	/* Disable alloc of free bandwidth */
#define TXA_START_RC	BIT_3S	/* Start sync Rate Control */
#define TXA_STOP_RC		BIT_2S	/* Stop  sync Rate Control */
#define TXA_ENA_ARB		BIT_1S	/* Enable  Tx Arbiter */
#define TXA_DIS_ARB		BIT_0S	/* Disable Tx Arbiter */

/*	TXA_TEST	 8 bit	Tx Arbiter Test Register */
								/* Bit 7.. 6:	reserved */
#define TXA_INT_T_ON	BIT_5S	/* Tx Arb Interval Timer Test On */
#define TXA_INT_T_OFF	BIT_4S	/* Tx Arb Interval Timer Test Off */
#define TXA_INT_T_STEP	BIT_3S	/* Tx Arb Interval Timer Step */
#define TXA_LIM_T_ON	BIT_2S	/* Tx Arb Limit Timer Test On */
#define TXA_LIM_T_OFF	BIT_1S	/* Tx Arb Limit Timer Test Off */
#define TXA_LIM_T_STEP	BIT_0S	/* Tx Arb Limit Timer Step */

/*	TXA_STAT	 8 bit	Tx Arbiter Status Register */
								/* Bit 7.. 1:	reserved */
#define TXA_PRIO_XS		BIT_0S	/* sync queue has prio to send */

/*	Q_BC	32 bit	Current Byte Counter */
								/* Bit 31..16:	reserved */
#define BC_MAX			0xffff	/* Bit 15.. 0:	Byte counter */

/* BMU Control Status Registers */
/*	B0_R1_CSR	32 bit	BMU Ctrl/Stat Rx Queue 1 */
/*	B0_R2_CSR	32 bit	BMU Ctrl/Stat Rx Queue 2 */
/*	B0_XA1_CSR	32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
/*	B0_XS1_CSR	32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
/*	B0_XA2_CSR	32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
/*	B0_XS2_CSR	32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
/*	Q_CSR		32 bit	BMU Control/Status Register */
								/* Bit 31..25:	reserved */
#define CSR_SV_IDLE		BIT_24		/* BMU SM Idle */
								/* Bit 23..22:	reserved */
#define CSR_DESC_CLR	BIT_21		/* Clear Reset for Descr */
#define CSR_DESC_SET	BIT_20		/* Set   Reset for Descr */
#define CSR_FIFO_CLR	BIT_19		/* Clear Reset for FIFO */
#define CSR_FIFO_SET	BIT_18		/* Set   Reset for FIFO */
#define CSR_HPI_RUN		BIT_17		/* Release HPI SM */
#define CSR_HPI_RST		BIT_16		/* Reset   HPI SM to Idle */
#define CSR_SV_RUN		BIT_15		/* Release Supervisor SM */
#define CSR_SV_RST		BIT_14		/* Reset   Supervisor SM */
#define CSR_DREAD_RUN	BIT_13		/* Release Descr Read SM */
#define CSR_DREAD_RST	BIT_12		/* Reset   Descr Read SM */
#define CSR_DWRITE_RUN	BIT_11		/* Release Descr Write SM */
#define CSR_DWRITE_RST	BIT_10		/* Reset   Descr Write SM */
#define CSR_TRANS_RUN	BIT_9		/* Release Transfer SM */
#define CSR_TRANS_RST	BIT_8		/* Reset   Transfer SM */
#define CSR_ENA_POL		BIT_7		/* Enable  Descr Polling */
#define CSR_DIS_POL		BIT_6		/* Disable Descr Polling */
#define CSR_STOP		BIT_5		/* Stop  Rx/Tx Queue */
#define CSR_START		BIT_4		/* Start Rx/Tx Queue */
#define CSR_IRQ_CL_P	BIT_3		/* (Rx)	Clear Parity IRQ */
#define CSR_IRQ_CL_B	BIT_2		/* Clear EOB IRQ */
#define CSR_IRQ_CL_F	BIT_1		/* Clear EOF IRQ */
#define CSR_IRQ_CL_C	BIT_0		/* Clear ERR IRQ */

#define CSR_SET_RESET	(CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
						CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
						CSR_TRANS_RST)
#define CSR_CLR_RESET	(CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
						CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
						CSR_TRANS_RUN)

/*	Q_F	32 bit	Flag Register */
									/* Bit 31..28:	reserved */
#define F_ALM_FULL		BIT_27		/* Rx FIFO: almost full */
#define F_EMPTY			BIT_27		/* Tx FIFO: empty flag */
#define F_FIFO_EOF		BIT_26		/* Tag (EOF Flag) bit in FIFO */
#define F_WM_REACHED	BIT_25		/* Watermark reached */
									/* reserved */
#define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 23..16:	# of Qwords in FIFO */
									/* Bit 15..11: 	reserved */
#define F_WATER_MARK	0x0007ffL	/* Bit 10.. 0:	Watermark */

/*	Q_T1	32 bit	Test Register 1 */
/*		Holds four State Machine control Bytes */
#define SM_CRTL_SV_MSK	(0xffL<<24)	/* Bit 31..24:	Control Supervisor SM */
#define SM_CRTL_RD_MSK	(0xffL<<16)	/* Bit 23..16:	Control Read Desc SM */
#define SM_CRTL_WR_MSK	(0xffL<<8)	/* Bit 15.. 8:	Control Write Desc SM */
#define SM_CRTL_TR_MSK	0xffL		/* Bit	7.. 0:	Control Transfer SM */

/*	Q_T1_TR	 8 bit	Test Register 1 Transfer SM */
/*	Q_T1_WR	 8 bit	Test Register 1 Write Descriptor SM */
/*	Q_T1_RD	 8 bit	Test Register 1 Read Descriptor SM */
/*	Q_T1_SV	 8 bit	Test Register 1 Supervisor SM */

/* The control status byte of each machine looks like ... */
#define SM_STATE		0xf0	/* Bit 7.. 4:	State which shall be loaded */
#define SM_LOAD			BIT_3S	/* Load the SM with SM_STATE */
#define SM_TEST_ON		BIT_2S	/* Switch on SM Test Mode */
#define SM_TEST_OFF		BIT_1S	/* Go off the Test Mode */
#define SM_STEP			BIT_0S	/* Step the State Machine */
/* The encoding of the states is not supported by the Diagnostics Tool */

/*	Q_T2	32 bit	Test Register 2	*/
								/* Bit 31.. 8:	reserved */
#define T2_AC_T_ON		BIT_7	/* Address Counter Test Mode on */
#define T2_AC_T_OFF		BIT_6	/* Address Counter Test Mode off */
#define T2_BC_T_ON		BIT_5	/* Byte Counter Test Mode on */
#define T2_BC_T_OFF		BIT_4	/* Byte Counter Test Mode off */
#define T2_STEP04		BIT_3	/* Inc AC/Dec BC by 4 */
#define T2_STEP03		BIT_2	/* Inc AC/Dec BC by 3 */
#define T2_STEP02		BIT_1	/* Inc AC/Dec BC by 2 */
#define T2_STEP01		BIT_0	/* Inc AC/Dec BC by 1 */

/*	Q_T3	32 bit	Test Register 3	*/
								/* Bit 31.. 7:	reserved */
#define T3_MUX_MSK		(7<<4)	/* Bit  6.. 4:	Mux Position */
								/* Bit  3:	reserved */
#define T3_VRAM_MSK		7		/* Bit  2.. 0:	Virtual RAM Buffer Address */

/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
/*	RB_START	32 bit	RAM Buffer Start Address */
/*	RB_END		32 bit	RAM Buffer End Address */
/*	RB_WP		32 bit	RAM Buffer Write Pointer */
/*	RB_RP		32 bit	RAM Buffer Read Pointer */
/*	RB_RX_UTPP	32 bit	Rx Upper Threshold, Pause Pack */
/*	RB_RX_LTPP	32 bit	Rx Lower Threshold, Pause Pack */
/*	RB_RX_UTHP	32 bit	Rx Upper Threshold, High Prio */
/*	RB_RX_LTHP	32 bit	Rx Lower Threshold, High Prio */
/*	RB_PC		32 bit	RAM Buffer Packet Counter */
/*	RB_LEV		32 bit	RAM Buffer Level Register */
				/* Bit 31..19:	reserved */
#define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */

/*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
								/* Bit 7.. 4:	reserved */
#define RB_PC_DEC		BIT_3S	/* Packet Counter Decrem */
#define RB_PC_T_ON		BIT_2S	/* Packet Counter Test On */
#define RB_PC_T_OFF		BIT_1S	/* Packet Counter Tst Off */
#define RB_PC_INC		BIT_0S	/* Packet Counter Increm */

/*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
							/* Bit 7:	reserved */
#define RB_WP_T_ON		BIT_6S	/* Write Pointer Test On */
#define RB_WP_T_OFF		BIT_5S	/* Write Pointer Test Off */
#define RB_WP_INC		BIT_4S	/* Write Pointer Increm */
								/* Bit 3:	reserved */
#define RB_RP_T_ON		BIT_2S	/* Read Pointer Test On */
#define RB_RP_T_OFF		BIT_1S	/* Read Pointer Test Off */
#define RB_RP_DEC		BIT_0S	/* Read Pointer Decrement */

/*	RB_CTRL			 8 bit	RAM Buffer Control Register */
								/* Bit 7.. 6:	reserved */
#define RB_ENA_STFWD	BIT_5S	/* Enable  Store & Forward */
#define RB_DIS_STFWD	BIT_4S	/* Disable Store & Forward */
#define RB_ENA_OP_MD	BIT_3S	/* Enable  Operation Mode */
#define RB_DIS_OP_MD	BIT_2S	/* Disable Operation Mode */
#define RB_RST_CLR		BIT_1S	/* Clear RAM Buf STM Reset */
#define RB_RST_SET		BIT_0S	/* Set   RAM Buf STM Reset */


/* Receive and Transmit MAC FIFO Registers (GENESIS only) */

/*	RX_MFF_EA	32 bit	Receive MAC FIFO End Address */
/*	RX_MFF_WP	32 bit 	Receive MAC FIFO Write Pointer */
/*	RX_MFF_RP	32 bit	Receive MAC FIFO Read Pointer */
/*	RX_MFF_PC	32 bit	Receive MAC FIFO Packet Counter */
/*	RX_MFF_LEV	32 bit	Receive MAC FIFO Level */
/*	TX_MFF_EA	32 bit	Transmit MAC FIFO End Address */
/*	TX_MFF_WP	32 bit 	Transmit MAC FIFO Write Pointer */
/*	TX_MFF_WSP	32 bit	Transmit MAC FIFO WR Shadow Pointer */
/*	TX_MFF_RP	32 bit	Transmit MAC FIFO Read Pointer */
/*	TX_MFF_PC	32 bit	Transmit MAC FIFO Packet Cnt */
/*	TX_MFF_LEV	32 bit	Transmit MAC FIFO Level */
								/* Bit 31.. 6:	reserved */
#define MFF_MSK			0x007fL	/* Bit	5.. 0:	MAC FIFO Address/Ptr Bits */

/*	RX_MFF_CTRL1	16 bit	Receive MAC FIFO Control Reg 1 */
								/* Bit 15..14:	reserved */
#define MFF_ENA_RDY_PAT	BIT_13S		/* Enable  Ready Patch */
#define MFF_DIS_RDY_PAT	BIT_12S		/* Disable Ready Patch */
#define MFF_ENA_TIM_PAT	BIT_11S		/* Enable  Timing Patch */
#define MFF_DIS_TIM_PAT	BIT_10S		/* Disable Timing Patch */
#define MFF_ENA_ALM_FUL	BIT_9S		/* Enable  AlmostFull Sig