skgehw.h

适合KS8695X

/******************************************************************************
 *
 * Name:	skgehw.h
 * Project:	GEnesis, PCI Gigabit Ethernet Adapter
 * Version:	$Revision: 1.49 $
 * Date:	$Date: 2003/01/28 09:43:49 $
 * Purpose:	Defines and Macros for the Gigabit Ethernet Adapter Product Family
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	(C)Copyright 1998-2003 SysKonnect GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/******************************************************************************
 *
 * History:
 * $Log: skgehw.h,v $
 * Revision 1.49  2003/01/28 09:43:49  rschmidt
 * Added defines for PCI-Spec. 2.3 IRQ
 * Added defines for CLK_RUN (YUKON-Lite)
 * Editorial changes
 *
 * Revision 1.48  2002/12/05 10:25:11  rschmidt
 * Added defines for Half Duplex Burst Mode On/Off
 * Added defines for Rx GMAC FIFO Flush feature
 * Editorial changes
 *
 * Revision 1.47  2002/11/12 17:01:31  rschmidt
 * Added defines for WOL_CTL_DEFAULT
 * Editorial changes
 *
 * Revision 1.46  2002/10/14 14:47:57  rschmidt
 * Corrected bit mask for HW self test results
 * Added defines for WOL Registers
 * Editorial changes
 *
 * Revision 1.45  2002/10/11 09:25:22  mkarl
 * Added bit mask for HW self test results.
 *
 * Revision 1.44  2002/08/16 14:44:36  rschmidt
 * Added define GPC_HWCFG_GMII_FIB for YUKON Fiber
 *
 * Revision 1.43  2002/08/12 13:31:50  rschmidt
 * Corrected macros for GMAC Address Registers: GM_INADDR(),
 * GM_OUTADDR(), GM_INHASH, GM_OUTHASH.
 * Editorial changes
 *
 * Revision 1.42  2002/08/08 15:37:56  rschmidt
 * Added defines for Power Management Capabilities
 * Editorial changes
 *
 * Revision 1.41  2002/07/23 16:02:25  rschmidt
 * Added macro WOL_REG() to access WOL reg. (HW-Bug in YUKON 1st rev.)
 *
 * Revision 1.40  2002/07/15 15:41:37  rschmidt
 * Added new defines for Power Management Cap. & Control
 * Editorial changes
 *
 * Revision 1.39  2002/06/10 09:37:07  rschmidt
 * Added macros for the ADDR-Modul
 *
 * Revision 1.38  2002/06/05 08:15:19  rschmidt
 * Added defines for WOL Registers
 * Editorial changes
 *
 * Revision 1.37  2002/04/25 11:39:23  rschmidt
 * Added new defines for PCI Our Register 1
 * Added new registers and defines for YUKON (Rx FIFO, Tx FIFO,
 * Time Stamp Timer, GMAC Control, GPHY Control,Link Control,
 * GMAC IRQ Source and Mask, Wake-up Frame Pattern Match);
 * Added new defines for Control/Status (VAUX available)
 * Added Chip ID for YUKON
 * Added define for descriptors with UDP ext. for YUKON
 * Added macros to access the GMAC
 * Added new Phy Type for Marvell 88E1011S (GPHY)
 * Editorial changes
 *
 * Revision 1.36  2000/11/09 12:32:49  rassmann
 * Renamed variables.
 *
 * Revision 1.35  2000/05/19 10:17:13  cgoos
 * Added inactivity check in PHY_READ (in DEBUG mode only).
 *
 * Revision 1.34  1999/11/22 13:53:40  cgoos
 * Changed license header to GPL.
 *
 * Revision 1.33  1999/08/27 11:17:10  malthoff
 * It's more savely to put brackets around macro parameters.
 * Brackets added for PHY_READ and PHY_WRITE.
 *
 * Revision 1.32  1999/05/19 07:31:01  cgoos
 * Changes for 1000Base-T.
 * Added HWAC_LINK_LED macro.
 *
 * Revision 1.31  1999/03/12 13:27:40  malthoff
 * Remove __STDC__.
 *
 * Revision 1.30  1999/02/09 09:28:20  malthoff
 * Add PCI_ERRBITS.
 *
 * Revision 1.29  1999/01/26 08:55:48  malthoff
 * Bugfix: The 16 bit field relations inside the descriptor are
 * 	endianess dependend if the descriptor reversal feature
 * 	(PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled.
 * 	Drivers which use this feature has to set the define
 * 	SK_USE_REV_DESC.
 *
 * Revision 1.28  1998/12/10 11:10:22  malthoff
 * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted.
 *
 * Revision 1.27  1998/11/13 14:19:21  malthoff
 * Bug Fix: The bit definition of B3_PA_CTRL has completely
 * changed from HW Spec v1.3 to v1.5.
 *
 * Revision 1.26  1998/11/04 08:31:48  cgoos
 * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros.
 *
 * Revision 1.25  1998/11/04 07:16:25  cgoos
 * Changed byte ordering in XM_INADDR/XM_INHASH again.
 *
 * Revision 1.24  1998/11/02 11:08:43  malthoff
 * RxCtrl and TxCtrl must be volatile.
 *
 * Revision 1.23  1998/10/28 13:50:45  malthoff
 * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros.
 *
 * Revision 1.22  1998/10/26 08:01:36  malthoff
 * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1,
 * RX_MFF_STAT_TO, and RX_MFF_TIST_TO.
 * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF.
 *
 * Revision 1.21  1998/10/20 07:43:10  malthoff
 * Fix: XM_IN/OUT/ADDR/HASH macros:
 * The pointer must be casted.
 *
 * Revision 1.20  1998/10/19 15:53:59  malthoff
 * Remove ML proto definitions.
 *
 * Revision 1.19  1998/10/16 14:40:17  gklug
 * fix: typo B0_XM_IMSK regs
 *
 * Revision 1.18  1998/10/16 09:46:54  malthoff
 * Remove temp defines for ML diag prototype.
 * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA
 * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR,
 * B0_XS2_CSR, and B0_XA2_CSR.
 *
 * Revision 1.17  1998/10/14 06:03:14  cgoos
 * Changed shifted constant to ULONG.
 *
 * Revision 1.16  1998/10/09 07:05:41  malthoff
 * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL.
 *
 * Revision 1.15  1998/10/05 07:54:23  malthoff
 * Split up RB_CTRL and it's bit definition into
 * RB_CTRL, RB_TST1, and RB_TST2.
 * Rename RB_RX_HTPP to RB_RX_LTPP.
 * Add ALL_PA_ENA_TO. Modify F_WATER_MARK
 * according to HW Spec. v1.5.
 * Add MFF_TX_CTRL_DEF.
 *
 * Revision 1.14  1998/09/28 13:31:16  malthoff
 * bug fix: B2_MAC_3 is 0x110 not 0x114
 *
 * Revision 1.13  1998/09/24 14:42:56  malthoff
 * Split the RX_MFF_TST into RX_MFF_CTRL2,
 * RX_MFF_TST1, and RX_MFF_TST2.
 * Rename RX_MFF_CTRL to RX_MFF_CTRL1.
 * Add BMU bit CSR_SV_IDLE.
 * Add macros PHY_READ() and PHY_WRITE().
 * Rename macro SK_ADDR() to SK_HW_ADDR()
 * because of conflicts with the Address Module.
 *
 * Revision 1.12  1998/09/16 07:25:33  malthoff
 * Change the parameter order in the XM_INxx and XM_OUTxx macros,
 * to have the IoC as first parameter.
 *
 * Revision 1.11  1998/09/03 09:58:41  malthoff
 * Rework the XM_xxx macros. Use {} instead of () to
 * be compatible with SK_xxx macros which are defined
 * with {}.
 *
 * Revision 1.10  1998/09/02 11:16:39  malthoff
 * Temporary modify B2_I2C_SW to make tests with
 * the GE/ML prototype.
 *
 * Revision 1.9  1998/08/19 09:11:49  gklug
 * fix: struct are removed from c-source (see CCC)
 * add: typedefs for all structs
 *
 * Revision 1.8  1998/08/18 08:27:27  malthoff
 * Add some temporary workarounds to test GE
 * sources with the ML.
 *
 * Revision 1.7  1998/07/03 14:42:26  malthoff
 * bug fix: Correct macro XMA().
 * Add temporary workaround to access the PCI config space over I/O
 *
 * Revision 1.6  1998/06/23 11:30:36  malthoff
 * Remove ';' with ',' in macors.
 *
 * Revision 1.5  1998/06/22 14:20:57  malthoff
 * Add macro SK_ADDR(Base,Addr).
 *
 * Revision 1.4  1998/06/19 13:35:43  malthoff
 * change 'pGec' with 'pAC'
 *
 * Revision 1.3  1998/06/17 14:58:16  cvs
 * Lost keywords reinserted.
 *
 * Revision 1.1  1998/06/17 14:16:36  cvs
 * created
 *
 *
 ******************************************************************************/

#ifndef __INC_SKGEHW_H
#define __INC_SKGEHW_H

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

#define BIT_31		(1UL << 31)
#define BIT_30		(1L << 30)
#define BIT_29		(1L << 29)
#define BIT_28		(1L << 28)
#define BIT_27		(1L << 27)
#define BIT_26		(1L << 26)
#define BIT_25		(1L << 25)
#define BIT_24		(1L << 24)
#define BIT_23		(1L << 23)
#define BIT_22		(1L << 22)
#define BIT_21		(1L << 21)
#define BIT_20		(1L << 20)
#define BIT_19		(1L << 19)
#define BIT_18		(1L << 18)
#define BIT_17		(1L << 17)
#define BIT_16		(1L << 16)
#define BIT_15		(1L << 15)
#define BIT_14		(1L << 14)
#define BIT_13		(1L << 13)
#define BIT_12		(1L << 12)
#define BIT_11		(1L << 11)
#define BIT_10		(1L << 10)
#define BIT_9		(1L << 9)
#define BIT_8		(1L << 8)
#define BIT_7		(1L << 7)
#define BIT_6		(1L << 6)
#define BIT_5		(1L << 5)
#define BIT_4		(1L << 4)
#define BIT_3		(1L << 3)
#define BIT_2		(1L << 2)
#define BIT_1		(1L << 1)
#define BIT_0		1L

#define BIT_15S		(1U << 15)
#define BIT_14S		(1 << 14)
#define BIT_13S		(1 << 13)
#define BIT_12S		(1 << 12)
#define BIT_11S		(1 << 11)
#define BIT_10S		(1 << 10)
#define BIT_9S		(1 << 9)
#define BIT_8S		(1 << 8)
#define BIT_7S 		(1 << 7)
#define BIT_6S		(1 << 6)
#define BIT_5S		(1 << 5)
#define BIT_4S		(1 << 4)
#define BIT_3S		(1 << 3)
#define BIT_2S		(1 << 2)
#define BIT_1S		(1 << 1)
#define BIT_0S		1

#define SHIFT31(x)	((x) << 31)
#define SHIFT30(x)	((x) << 30)
#define SHIFT29(x)	((x) << 29)
#define SHIFT28(x)	((x) << 28)
#define SHIFT27(x)	((x) << 27)
#define SHIFT26(x)	((x) << 26)
#define SHIFT25(x)	((x) << 25)
#define SHIFT24(x)	((x) << 24)
#define SHIFT23(x)	((x) << 23)
#define SHIFT22(x)	((x) << 22)
#define SHIFT21(x)	((x) << 21)
#define SHIFT20(x)	((x) << 20)
#define SHIFT19(x)	((x) << 19)
#define SHIFT18(x)	((x) << 18)
#define SHIFT17(x)	((x) << 17)
#define SHIFT16(x)	((x) << 16)
#define SHIFT15(x)	((x) << 15)
#define SHIFT14(x)	((x) << 14)
#define SHIFT13(x)	((x) << 13)
#define SHIFT12(x)	((x) << 12)