xmac_ii.h

适合KS8695X

/******************************************************************************
 *
 * Name:	xmac_ii.h
 * Project:	GEnesis, PCI Gigabit Ethernet Adapter
 * Version:	$Revision: 1.46 $
 * Date:	$Date: 2003/01/28 09:47:45 $
 * Purpose:	Defines and Macros for Gigabit Ethernet Controller
 *
 ******************************************************************************/

/******************************************************************************
 *
 *	(C)Copyright 1998-2003 SysKonnect GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/******************************************************************************
 *
 * History:
 *
 *	$Log: xmac_ii.h,v $
 *	Revision 1.46  2003/01/28 09:47:45  rschmidt
 *	Added defines for copper MDI/MDIX configuration
 *	Added defines for LED Control Register
 *	Editorial changes
 *
 *	Revision 1.45  2002/12/10 14:35:13  rschmidt
 *	Corrected defines for Extended PHY Specific Control
 *	Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific)
 *
 *	Revision 1.44  2002/12/09 14:58:41  rschmidt
 *	Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature)
 *	Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask
 *
 *	Revision 1.43  2002/12/05 10:14:45  rschmidt
 *	Added define for GMAC's Half Duplex Burst Mode
 *	Added define for Rx GMAC FIFO Flush Mask (default)
 *
 *	Revision 1.42  2002/11/12 16:48:19  rschmidt
 *	Added defines for Cable Diagnostic Register (GPHY)
 *	Editorial changes
 *
 *	Revision 1.41  2002/10/21 11:20:22  rschmidt
 *	Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR
 *	Editorial changes
 *
 *	Revision 1.40  2002/10/14 14:54:14  rschmidt
 *	Added defines for GPHY Specific Status and GPHY Interrupt Status
 *	Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK
 *	Editorial changes
 *
 *	Revision 1.39  2002/10/10 15:53:44  mkarl
 *	added some bit definitions for link speed status and LED's
 *
 *	Revision 1.38  2002/08/21 16:23:46  rschmidt
 *	Added defines for PHY Specific Ctrl Reg
 *	Editorial changes
 *
 *	Revision 1.37  2002/08/16 14:50:33  rschmidt
 *	Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only)
 *	Changed define PHY_M_DEF_MSK for GPHY IRQ Mask
 *	Editorial changes
 *
 *	Revision 1.36  2002/08/12 13:21:10  rschmidt
 *	Added defines for different Broadcom PHY Ids
 *
 *	Revision 1.35  2002/08/08 15:58:01  rschmidt
 *	Added defines for Manual LED Override register (YUKON)
 *	Editorial changes
 *
 *	Revision 1.34  2002/07/31 17:23:36  rwahl
 *	Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR).
 *
 *	Revision 1.33  2002/07/23 16:03:37  rschmidt
 *	Added defines for GPHY registers
 *	Editorial changes
 *
 *	Revision 1.32  2002/07/15 18:14:37  rwahl
 *	Added GMAC MIB counters definitions.
 *	Editorial changes.
 *
 *	Revision 1.31  2002/07/15 15:42:50  rschmidt
 *	Removed defines from PHY specific reg. which are
 *	common to all PHYs
 *	Added defines for GMAC MIB Counters
 *	Editorial changes
 *
 *	Revision 1.30  2002/06/05 08:22:12  rschmidt
 *	Changed defines for GMAC Rx Control Register and Rx Status
 *	Editorial changes
 *
 *	Revision 1.29  2002/04/25 11:43:56  rschmidt
 *	Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res.
 *	Added new registers and defines for YUKON (GMAC, GPHY)
 *	Added Receive Frame Status Encoding for YUKON
 *	Editorial changes
 *
 *	Revision 1.28  2000/11/09 12:32:49  rassmann
 *	Renamed variables.
 *
 *	Revision 1.27  2000/05/17 11:00:46  malthoff
 *	Add bit for enable/disable power management in BCOM chip.
 *
 *	Revision 1.26  1999/11/22 14:03:00  cgoos
 *	Changed license header to GPL.
 *
 *	Revision 1.25  1999/08/12 19:19:38  malthoff
 *	Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet.
 *
 *	Revision 1.24  1999/07/30 11:27:21  cgoos
 *	Fixed a missing end-of-comment.
 *
 *	Revision 1.23  1999/07/30 07:03:31  malthoff
 *	Cut some long comments.
 *	Correct the XMAC PHY ID definitions.
 *
 *	Revision 1.22  1999/05/19 07:33:18  cgoos
 *	Changes for 1000Base-T.
 *
 *	Revision 1.21  1999/03/25 07:46:11  malthoff
 *	Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers.
 *
 *	Revision 1.20  1999/03/12 13:36:09  malthoff
 *	Remove __STDC__.
 *
 *	Revision 1.19  1998/12/10 12:22:54  gklug
 *	fix: RX_PAGE must be in interrupt mask
 *
 *	Revision 1.18  1998/12/10 10:36:36  gklug
 *	fix: swap of pause bits
 *
 *	Revision 1.17  1998/11/18 13:21:45  gklug
 *	fix: Default interrupt mask
 *
 *	Revision 1.16  1998/10/29 15:53:21  gklug
 *	fix: Default mask uses ASS (GP0) signal
 *
 *	Revision 1.15  1998/10/28 13:52:52  malthoff
 *	Add new bits in RX_CMD register.
 *
 *	Revision 1.14  1998/10/19 15:34:53  gklug
 *	fix: typos
 *
 *	Revision 1.13  1998/10/14 07:19:03  malthoff
 *	bug fix: Every define which describes bit 31
 *	must be declared as unsigned long 'UL'.
 *	fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE.
 *	Remove ANP defines. Rework the RFB defines.
 *
 *	Revision 1.12  1998/10/14 06:22:44  cgoos
 *	Changed shifted constant to ULONG.
 *
 *	Revision 1.11  1998/10/14 05:43:26  gklug
 *	add: shift pause coding
 *	fix: PAUSE bits definition
 *
 *	Revision 1.10  1998/10/13 09:19:21  malthoff
 *	Again change XMR_FS_ANY_ERR because of new info from XaQti.
 *
 *	Revision 1.9  1998/10/09 07:58:30  malthoff
 *	Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR.
 *
 *	Revision 1.8  1998/10/09 07:18:17  malthoff
 *	bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE
 *	are not inverted! Bug XM_DEF_MSK is inverted.
 *
 *	Revision 1.7  1998/10/05 08:04:32  malthoff
 *	bug fix: XM_PAUSE_MODE and XM_DEF_MODE
 *	must be inverted declarations.
 *
 *	Revision 1.6  1998/09/28 13:38:18  malthoff
 *	Add default modes and masks XM_DEF_MSK,
 *	XM_PAUSE_MODE and XM_DEF_MODE
 *
 *	Revision 1.5  1998/09/16 14:42:04  malthoff
 *	Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register.
 *
 *	Revision 1.4  1998/08/20 14:59:47  malthoff
 *	Rework this file after reading the XaQti data sheet
 *	"Differences between Rev. B2 & Rev. C XMAC II".
 *	This file is now 100% XMAC II Rev. C complained.
 *
 *	Revision 1.3  1998/06/29 12:18:23  malthoff
 *	Correct XMR_FS_ANY_ERR definition.
 *
 *	Revision 1.2  1998/06/29 12:10:56  malthoff
 *	Add define XMR_FS_ANY_ERR.
 *
 *	Revision 1.1  1998/06/19 13:37:17  malthoff
 *	created.
 *
 *
 ******************************************************************************/

#ifndef __INC_XMAC_H
#define __INC_XMAC_H

#ifdef __cplusplus
extern "C" {
#endif	/* __cplusplus */

/* defines ********************************************************************/

/*
 * XMAC II registers
 *
 * The XMAC registers are 16 or 32 bits wide.
 * The XMACs host processor interface is set to 16 bit mode,
 * therefore ALL registers will be addressed with 16 bit accesses.
 *
 * The following macros are provided to access the XMAC registers
 * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(),
 * XM_INHASH(), and XM_OUTHASH().
 * The macros are defined in SkGeHw.h.
 *
 * Note:	NA reg	= Network Address e.g DA, SA etc.
 *
 */
#define XM_MMU_CMD		0x0000	/* 16 bit r/w	MMU Command Register */
	/* 0x0004:		reserved */
#define XM_POFF			0x0008	/* 32 bit r/w	Packet Offset Register */
#define XM_BURST		0x000c	/* 32 bit r/w	Burst Register for half duplex*/
#define XM_1L_VLAN_TAG	0x0010	/* 16 bit r/w	One Level VLAN Tag ID */
#define XM_2L_VLAN_TAG	0x0014	/* 16 bit r/w	Two Level VLAN Tag ID */
	/* 0x0018 - 0x001e:	reserved */
#define XM_TX_CMD		0x0020	/* 16 bit r/w	Transmit Command Register */
#define XM_TX_RT_LIM	0x0024	/* 16 bit r/w	Transmit Retry Limit Register */
#define XM_TX_STIME		0x0028	/* 16 bit r/w	Transmit Slottime Register */
#define XM_TX_IPG		0x002c	/* 16 bit r/w	Transmit Inter Packet Gap */
#define XM_RX_CMD		0x0030	/* 16 bit r/w	Receive Command Register */
#define XM_PHY_ADDR		0x0034	/* 16 bit r/w	PHY Address Register */
#define XM_PHY_DATA		0x0038	/* 16 bit r/w	PHY Data Register */
	/* 0x003c: 		reserved */
#define XM_GP_PORT		0x0040	/* 32 bit r/w	General Purpose Port Register */
#define XM_IMSK			0x0044	/* 16 bit r/w	Interrupt Mask Register */
#define XM_ISRC			0x0048	/* 16 bit r/o	Interrupt Status Register */
#define XM_HW_CFG		0x004c	/* 16 bit r/w	Hardware Config Register */
	/* 0x0050 - 0x005e:	reserved */
#define XM_TX_LO_WM		0x0060	/* 16 bit r/w	Tx FIFO Low Water Mark */
#define XM_TX_HI_WM		0x0062	/* 16 bit r/w	Tx FIFO High Water Mark */
#define XM_TX_THR		0x0064	/* 16 bit r/w	Tx Request Threshold */
#define XM_HT_THR		0x0066	/* 16 bit r/w	Host Request Threshold */
#define XM_PAUSE_DA		0x0068	/* NA reg r/w	Pause Destination Address */
	/* 0x006e: 		reserved */
#define XM_CTL_PARA		0x0070	/* 32 bit r/w	Control Parameter Register */
#define XM_MAC_OPCODE	0x0074	/* 16 bit r/w	Opcode for MAC control frames */
#define XM_MAC_PTIME	0x0076	/* 16 bit r/w	Pause time for MAC ctrl frames*/
#define XM_TX_STAT		0x0078	/* 32 bit r/o	Tx Status LIFO Register */

	/* 0x0080 - 0x00fc:	16 NA reg r/w	Exact Match Address Registers */
	/* 				use the XM_EXM() macro to address */
#define XM_EXM_START	0x0080	/* r/w	Start Address of the EXM Regs */

	/*
	 * XM_EXM(Reg)