readme.txt

SMSC9118网卡驱动

118 driver for EDGE Interrupt to GPIO44

2006-08-25 This is the second checkin of the direct interrupt supported version going forward from Version 1.08.  As delivered, the global symbol SMSC_DIRECT_INTR found in xscale-50.h is #undef.  To enable useage, change the #undef to a #define.  Also note that for the direct interrupt code to run on the Mainstone platform, there are KERNEL changes required to complete the change-over to direct interrupt support.
The problem of losing interrupts from the SMSC9218 in Intel Xscale-based CPU designs arises from the manner that Mainstone II WinCE board support package (BSP) disables interrupts for its own usage.  For the typical CPU that deals with level-triggered interrupts, there is generally an associated mask bit and a status bit that get logically AND-ed together.  If the mask bit is set (interrupt is enabled) and the IRQ status goes active, the AND-ing of the two signals drives the interrupt input of the CPU, causing an interrupt handler to run.  If the mask bit is cleared, the interrupt is disabled.

For the Mainstone BSP, this is achieved by clearing the XScale internal GPIO Falling Edge detect Register (GFER) bit associated with the 9218 IRQ.  Once cleared, should the 9218 IRQ signal go active during the period that the associated GFER bit is clear; the falling edge is not detected and therefore is missed.  Thereafter the active IRQ will never trigger an interrupt to the XScale.