📄 lan9118.h
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#define RX_CFG_RX_END_ALGN32_ (0x80000000UL) // R/W
#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000UL) // R/W
#define RX_CFG_RX_DUMP_ (0x00008000UL) // R/W
#define RX_CFG_RXDOFF_ (0x00001F00UL) // R/W
#define RX_CFG_RXBAD_ (0x00000001UL) // R/W
#define TX_CFG (0x70UL)
#define TX_CFG_TX_DMA_LVL_ (0xE0000000UL) // R/W
#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000UL) // R/W Self Clearing
#define TX_CFG_TXS_DUMP_ (0x00008000UL) // Self Clearing
#define TX_CFG_TXD_DUMP_ (0x00004000UL) // Self Clearing
#define TX_CFG_TXSAO_ (0x00000004UL) // R/W
#define TX_CFG_TX_ON_ (0x00000002UL) // R/W
#define TX_CFG_STOP_TX_ (0x00000001UL) // Self Clearing
#define HW_CFG (0x74UL)
#define HW_CFG_AMDIX_EN_STS_ (0x01000000UL) // R/O
#define HW_CFG_TTM_ (0x00200000UL) // R/W
#define HW_CFG_SF_ (0x00100000UL) // R/W
#define HW_CFG_TX_FIF_SZ_ (0x000F0000UL) // R/W
#define HW_CFG_TR_ (0x00003000UL) // R/W
#define HW_CFG_PHY_CLK_SEL_ (0x00000060UL) // R/W
#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000UL) // R/W
#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020UL) // R/W
#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040UL) // R/W
#define HW_CFG_SMI_SEL_ (0x00000010UL) // R/W
#define HW_CFG_EXT_PHY_DET_ (0x00000008UL) // RO
#define HW_CFG_EXT_PHY_EN_ (0x00000004UL) // R/W
#define HW_CFG_SRST_TO_ (0x00000002UL) // RO
#define HW_CFG_SRST_ (0x00000001UL) // Self Clearing
#define RX_DP_CTL (0x78UL)
#define RX_DP_CTL_FFWD_BUSY_ (0x80000000UL) // R/?
#define RX_DP_CTL_RX_FFWD_ (0x00000FFFUL) // R/W
#define RX_FIFO_INF (0x7CUL)
#define RX_FIFO_INF_RXSUSED_ (0x00FF0000UL) // RO
#define RX_FIFO_INF_RXDUSED_ (0x0000FFFFUL) // RO
#define TX_FIFO_INF (0x80UL)
#define TX_FIFO_INF_TSFREE_ (0x00FF0000UL) // RO for PAS V.1.3
#define TX_FIFO_INF_TSUSED_ (0x00FF0000UL) // RO for PAS V.1.4
#define TX_FIFO_INF_TDFREE_ (0x0000FFFFUL) // RO
#define PMT_CTRL (0x84UL)
#define PMT_CTRL_PM_MODE_ (0x00003000UL) // Self Clearing
#define PMT_CTRL_PM_MODE_GP_ (0x00003000UL) // Self Clearing
#define PMT_CTRL_PM_MODE_ED_ (0x00002000UL) // Self Clearing
#define PMT_CTRL_PM_MODE_WOL_ (0x00001000UL) // Self Clearing
#define PMT_CTRL_PHY_RST_ (0x00000400UL) // Self Clearing
#define PMT_CTRL_WOL_EN_ (0x00000200UL) // R/W
#define PMT_CTRL_ED_EN_ (0x00000100UL) // R/W
#define PMT_CTRL_PME_TYPE_ (0x00000040UL) // R/W Not Affected by SW Reset
#define PMT_CTRL_WUPS_ (0x00000030UL) // R/WC
#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000UL) // R/WC
#define PMT_CTRL_WUPS_ED_ (0x00000010UL) // R/WC
#define PMT_CTRL_WUPS_WOL_ (0x00000020UL) // R/WC
#define PMT_CTRL_WUPS_MULTI_ (0x00000030UL) // R/WC
#define PMT_CTRL_PME_IND_ (0x00000008UL) // R/W
#define PMT_CTRL_PME_POL_ (0x00000004UL) // R/W
#define PMT_CTRL_PME_EN_ (0x00000002UL) // R/W Not Affected by SW Reset
#define PMT_CTRL_READY_ (0x00000001UL) // RO
#define GPIO_CFG (0x88UL)
#define GPIO_CFG_LED3_EN_ (0x40000000UL) // R/W
#define GPIO_CFG_LED2_EN_ (0x20000000UL) // R/W
#define GPIO_CFG_LED1_EN_ (0x10000000UL) // R/W
#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000UL) // R/W
#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000UL) // R/W
#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000UL) // R/W
#define GPIO_CFG_EEPR_EN_ (0x00700000UL) // R/W
#define GPIO_CFG_GPIOBUF2_ (0x00040000UL) // R/W
#define GPIO_CFG_GPIOBUF1_ (0x00020000UL) // R/W
#define GPIO_CFG_GPIOBUF0_ (0x00010000UL) // R/W
#define GPIO_CFG_GPIODIR2_ (0x00000400UL) // R/W
#define GPIO_CFG_GPIODIR1_ (0x00000200UL) // R/W
#define GPIO_CFG_GPIODIR0_ (0x00000100UL) // R/W
#define GPIO_CFG_GPIOD4_ (0x00000020UL) // R/W
#define GPIO_CFG_GPIOD3_ (0x00000010UL) // R/W
#define GPIO_CFG_GPIOD2_ (0x00000004UL) // R/W
#define GPIO_CFG_GPIOD1_ (0x00000002UL) // R/W
#define GPIO_CFG_GPIOD0_ (0x00000001UL) // R/W
#define GPT_CFG (0x8CUL)
#define GPT_CFG_TIMER_EN_ (0x20000000UL) // R/W
#define GPT_CFG_GPT_LOAD_ (0x0000FFFFUL) // R/W
#define GPT_CNT (0x90UL)
#define GPT_CNT_GPT_CNT_ (0x0000FFFFUL) // RO
#define FPGA_REV (0x94UL)
#define FPGA_REV_FPGA_REV_ (0x0000FFFFUL) // RO
#define ENDIAN (0x98UL) // R/W Not Affected by SW Reset
#define FREE_RUN (0x9CUL) // RO
#define RX_DROP (0xA0UL) // R/WC
#define MAC_CSR_CMD (0xA4UL)
#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000UL) // Self Clearing
#define MAC_CSR_CMD_R_NOT_W_ (0x40000000UL) // R/W
#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FFUL) // R/W
#define MAC_CSR_DATA (0xA8UL) // R/W
#define AFC_CFG (0xACUL)
#define AFC_CFG_AFC_HI_ (0x00FF0000UL) // R/W
#define AFC_CFG_AFC_LO_ (0x0000FF00UL) // R/W
#define AFC_CFG_BACK_DUR_ (0x000000F0UL) // R/W
#define AFC_CFG_FCMULT_ (0x00000008UL) // R/W
#define AFC_CFG_FCBRD_ (0x00000004UL) // R/W
#define AFC_CFG_FCADD_ (0x00000002UL) // R/W
#define AFC_CFG_FCANY_ (0x00000001UL) // R/W
#define E2P_CMD (0xB0UL)
#define E2P_CMD_EPC_BUSY_ (0x80000000UL) // Self Clearing
#define E2P_CMD_EPC_CMD_ (0x70000000UL) // R/W
#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) // R/W
#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) // R/W
#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) // R/W
#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) // R/W
#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) // R/W
#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) // R/W
#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) // R/W
#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) // R/W
#define E2P_CMD_EPC_TIMEOUT_ (0x08000000UL) // RO
#define E2P_CMD_E2P_PROG_GO_ (0x00000200UL) // WO
#define E2P_CMD_E2P_PROG_DONE_ (0x00000100UL) // RO
#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) // R/W
#define E2P_DATA (0xB4UL)
#define E2P_DATA_EEPROM_DATA_ (0x000000FFUL) // R/W
#define TEST_REG_A (0xC0UL)
#define TEST_REG_A_FR_CNT_BYP_ (0x00000008UL) // R/W
#define TEST_REG_A_PME50M_BYP_ (0x00000004UL) // R/W
#define TEST_REG_A_PULSE_BYP_ (0x00000002UL) // R/W
#define TEST_REG_A_PS_BYP_ (0x00000001UL) // R/W
#define LAN_REGISTER_EXTENT (0x00000100UL)
/*
****************************************************************************
****************************************************************************
* MAC Control and Status Register (Indirect Address)
* Offset (through the MAC_CSR CMD and DATA port)
****************************************************************************
****************************************************************************
*
*/
#define MAC_CR (0x01UL) // R/W
/* MAC_CR - MAC Control Register */
#define MAC_CR_RXALL_ (0x80000000UL)
#define MAC_CR_HBDIS_ (0x10000000UL)
#define MAC_CR_RCVOWN_ (0x00800000UL)
#define MAC_CR_LOOPBK_ (0x00200000UL)
#define MAC_CR_FDPX_ (0x00100000UL)
#define MAC_CR_MCPAS_ (0x00080000UL)
#define MAC_CR_PRMS_ (0x00040000UL)
#define MAC_CR_INVFILT_ (0x00020000UL)
#define MAC_CR_PASSBAD_ (0x00010000UL)
#define MAC_CR_HFILT_ (0x00008000UL)
#define MAC_CR_HPFILT_ (0x00002000UL)
#define MAC_CR_LCOLL_ (0x00001000UL)
#define MAC_CR_BCAST_ (0x00000800UL)
#define MAC_CR_DISRTY_ (0x00000400UL)
#define MAC_CR_PADSTR_ (0x00000100UL)
#define MAC_CR_BOLMT_MASK_ (0x000000C0UL)
#define MAC_CR_DFCHK_ (0x00000020UL)
#define MAC_CR_TXEN_ (0x00000008UL)
#define MAC_CR_RXEN_ (0x00000004UL)
#define ADDRH (0x02UL) // R/W mask 0x0000FFFFUL
#define ADDRL (0x03UL) // R/W mask 0xFFFFFFFFUL
#define HASHH (0x04UL) // R/W
#define HASHL (0x05UL) // R/W
#define MII_ACC (0x06UL) // R/W
#define MII_ACC_PHY_ADDR_ (0x0000F800UL)
#define MII_ACC_MIIRINDA_ (0x000007C0UL)
#define MII_ACC_MII_WRITE_ (0x00000002UL)
#define MII_ACC_MII_BUSY_ (0x00000001UL)
#define MII_DATA (0x07UL) // R/W mask 0x0000FFFFUL
#define FLOW (0x08UL) // R/W
#define FLOW_FCPT_ (0xFFFF0000UL)
#define FLOW_FCPASS_ (0x00000004UL)
#define FLOW_FCEN_ (0x00000002UL)
#define FLOW_FCBSY_ (0x00000001UL)
#define VLAN1 (0x09UL) // R/W mask 0x0000FFFFUL
#define VLAN2 (0x0AUL) // R/W mask 0x0000FFFFUL
#define WUFF (0x0BUL) // WO
#define FILTER3_COMMAND (0x0F000000UL)
#define FILTER2_COMMAND (0x000F0000UL)
#define FILTER1_COMMAND (0x00000F00UL)
#define FILTER0_COMMAND (0x0000000FUL)
#define FILTER3_ADDR_TYPE (0x04000000UL)
#define FILTER3_ENABLE (0x01000000UL)
#define FILTER2_ADDR_TYPE (0x00040000UL)
#define FILTER2_ENABLE (0x00010000UL)
#define FILTER1_ADDR_TYPE (0x00000400UL)
#define FILTER1_ENABLE (0x00000100UL)
#define FILTER0_ADDR_TYPE (0x00000004UL)
#define FILTER0_ENABLE (0x00000001UL)
#define FILTER3_OFFSET (0xFF000000UL)
#define FILTER2_OFFSET (0x00FF0000UL)
#define FILTER1_OFFSET (0x0000FF00UL)
#define FILTER0_OFFSET (0x000000FFUL)
#define FILTER3_CRC (0xFFFF0000UL)
#define FILTER2_CRC (0x0000FFFFUL)
#define FILTER1_CRC (0xFFFF0000UL)
#define FILTER0_CRC (0x0000FFFFUL)
#define WUCSR (0x0CUL) // R/W
#define WUCSR_GUE_ (0x00000200UL)
#define WUCSR_WUFR_ (0x00000040UL)
#define WUCSR_MPR_ (0x00000020UL)
#define WUCSR_WAKE_EN_ (0x00000004UL)
#define WUCSR_MPEN_ (0x00000002UL)
/*
****************************************************************************
* Chip Specific MII Defines
****************************************************************************
*
* Phy register offsets and bit definitions
*
*/
#define LAN9118_PHY_ID (0x00C0001CUL)
#define PHY_BCR ((DWORD)0U)
#define PHY_BCR_RESET_ ((WORD)0x8000U)
#define PHY_BCR_SPEED_SELECT_ ((WORD)0x2000U)
#define PHY_BCR_AUTO_NEG_ENABLE_ ((WORD)0x1000U)
#define PHY_BCR_POWER_DOWN_ ((WORD)0x0800U)
#define PHY_BCR_RESTART_AUTO_NEG_ ((WORD)0x0200U)
#define PHY_BCR_DUPLEX_MODE_ ((WORD)0x0100U)
#define PHY_BSR ((DWORD)1U)
#define PHY_BSR_LINK_STATUS_ ((WORD)0x0004U)
#define PHY_BSR_REMOTE_FAULT_ ((WORD)0x0010U)
#define PHY_BSR_AUTO_NEG_COMP_ ((WORD)0x0020U)
#define PHY_BSR_ANEG_ABILITY_ ((WORD)0x0008U)
#define PHY_ID_1 ((DWORD)2U)
#define PHY_ID_2 ((DWORD)3U)
#define PHY_ANEG_ADV ((DWORD)4U)
#define PHY_ANEG_ADV_PAUSE_OP_ ((WORD)0x0C00)
#define PHY_ANEG_ADV_ASYM_PAUSE_ ((WORD)0x0800)
#define PHY_ANEG_ADV_SYM_PAUSE_ ((WORD)0x0400)
#define PHY_ANEG_ADV_10H_ ((WORD)0x0020)
#define PHY_ANEG_ADV_10F_ ((WORD)0x0040)
#define PHY_ANEG_ADV_100H_ ((WORD)0x0080)
#define PHY_ANEG_ADV_100F_ ((WORD)0x0100)
#define PHY_ANEG_ADV_SPEED_ ((WORD)0x01E0)
#define PHY_ANEG_LPA ((DWORD)5U)
#define PHY_ANEG_LPA_100FDX_ ((WORD)0x0100)
#define PHY_ANEG_LPA_100HDX_ ((WORD)0x0080)
#define PHY_ANEG_LPA_10FDX_ ((WORD)0x0040)
#define PHY_ANEG_LPA_10HDX_ ((WORD)0x0020)
#define PHY_ANEG_EXP ((DWORD)6U)
#define PHY_ANEG_EXP_PDF_ ((WORD)0x0010)
#define PHY_ANEG_EXP_LPNPA_ ((WORD)0x0008)
#define PHY_ANEG_EXP_NPA_ ((WORD)0x0004)
#define PHY_ANEG_EXP_PAGE_RX_ ((WORD)0x0002)
#define PHY_ANEG_EXP_LPANEG_ABLE_ ((WORD)0x0001)
#define PHY_MODE_CTRL_STS ((DWORD)17) // Mode Control/Status Register
#define MODE_CTRL_STS_FASTRIP_ ((WORD)0x4000U)
#define MODE_CTRL_STS_EDPWRDOWN_ ((WORD)0x2000U)
#define MODE_CTRL_STS_LOWSQEN_ ((WORD)0x0800U)
#define MODE_CTRL_STS_MDPREBP_ ((WORD)0x0400U)
#define MODE_CTRL_STS_FARLOOPBACK_ ((WORD)0x0200U)
#define MODE_CTRL_STS_FASTEST_ ((WORD)0x0100U)
#define MODE_CTRL_STS_REFCLKEN_ ((WORD)0x0010U)
#define MODE_CTRL_STS_PHYADBP_ ((WORD)0x0008U)
#define MODE_CTRL_STS_FORCE_G_LINK_ ((WORD)0x0004U)
#define MODE_CTRL_STS_ENERGYON_ ((WORD)0x0002U)
#define PHY_CS_IND ((DWORD)27)
#define PHY_CS_IND_OVER_AMDIX_EN_ ((WORD)0x8000U)
#define PHY_CS_IND_AMDIX_EN_ ((WORD)0x4000U)
#define PHY_CS_IND_AMDIX_STS_ ((WORD)0x2000U)
#define PHY_INT_SRC ((DWORD)29)
#define PHY_INT_SRC_ENERGY_ON_ ((WORD)0x0080U)
#define PHY_INT_SRC_ANEG_COMP_ ((WORD)0x0040U)
#define PHY_INT_SRC_REMOTE_FAULT_ ((WORD)0x0020U)
#define PHY_INT_SRC_LINK_DOWN_ ((WORD)0x0010U)
#define PHY_INT_MASK ((DWORD)30)
#define PHY_INT_MASK_ENERGY_ON_ ((WORD)0x0080U)
#define PHY_INT_MASK_ANEG_COMP_ ((WORD)0x0040U)
#define PHY_INT_MASK_REMOTE_FAULT_ ((WORD)0x0020U)
#define PHY_INT_MASK_LINK_DOWN_ ((WORD)0x0010U)
#define PHY_SPECIAL ((DWORD)31)
#define PHY_SPECIAL_SPD_ ((WORD)0x001CU)
#define PHY_SPECIAL_SPD_10HALF_ ((WORD)0x0004U)
#define PHY_SPECIAL_SPD_10FULL_ ((WORD)0x0014U)
#define PHY_SPECIAL_SPD_100HALF_ ((WORD)0x0008U)
#define PHY_SPECIAL_SPD_100FULL_ ((WORD)0x0018U)
#endif
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