📄 lan9118.h
字号:
LINK_10MPS_HALF
LINK_10MPS_FULL
LINK_100MPS_HALF
LINK_100MPS_FULL
*/
DWORD Lan_GetLinkMode(const LAN9118_DATA * const pLan9118Data);
/*
FUNCTION: Lan_EnableInterrupt
Enables bits in INT_EN according to the set bits in dwMask
WARNING this has thread synchronization issues. Use with caution.
*/
void Lan_EnableInterrupt(const LAN9118_DATA * const pLan9118Data, const DWORD dwMask);
/*
FUNCTION: Lan_DisableInterrupt
Disables bits in INT_EN according to the set bits in dwMask
WARNING this has thread synchronization issues. Use with caution.
*/
void Lan_DisableInterrupt(const LAN9118_DATA * const pLan9118Data, const DWORD dwMask);
/*
FUNCTION: Lan_GetInterruptStatus
Reads and returns the value in the INT_STS register.
*/
DWORD Lan_GetInterruptStatus(const LAN9118_DATA * const pLan9118Data);
/*
FUNCTION: Lan_ClearInterruptStatus
Clears the bits in INT_STS according to the bits set in dwMask
*/
void Lan_ClearInterruptStatus(const LAN9118_DATA * const pLan9118Data, const DWORD dwMask);
/*
FUNCTION: Lan_EnableIRQ
Sets IRQ_EN in the INT_CFG registers.
WARNING this has thread synchronization issues. Use with caution.
*/
void Lan_EnableIRQ(const LAN9118_DATA * const pLan9118Data);
/*
FUNCTION: Lan_DisableIRQ
Clears IRQ_EN in the INT_CFG registers.
WARNING this has thread sychronization issues. Use with caution.
*/
void Lan_DisableIRQ(const LAN9118_DATA * const pLan9118Data);
/*
FUNCTION: Lan_InitializeInterrupts
Should be called after Lan_Initialize
Should be called before the ISR is registered.
*/
void Lan_InitializeInterrupts(LAN9118_DATA * const pLan9118Data, DWORD dwIntCfg);
/*
FUNCTION: Lan_EnableSoftwareInterrupt
Clears a flag in the LAN9118_DATA structure
Sets the SW_INT_EN bit of the INT_EN register
WARNING this has thread sychronization issues. Use with caution.
*/
void Lan_EnableSoftwareInterrupt(PLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_HandleSoftwareInterrupt
Disables the SW_INT_EN bit of the INT_EN register,
Clears the SW_INT in the INT_STS,
Sets a flag in the LAN9118_DATA structure
*/
void Lan_HandleSoftwareInterrupt(PLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_IsSoftwareInterruptSignaled
returns the set/cleared state of the flag used in
Lan_EnableSoftwareInterrupt
Lan_HandleSoftwareInterrupt
*/
BOOLEAN Lan_IsSoftwareInterruptSignaled(const LAN9118_DATA * const pLan9118Data);
/*
FUNCTION: Lan_SetMacAddress, Lan_GetMacAddress
gets/sets the Mac Address
*/
void Lan_SetMacAddress(PLAN9118_DATA const pLan9118Data, const DWORD dwHigh16, const DWORD dwLow32);
void Lan_GetMacAddress(PLAN9118_DATA const pLan9118Data, DWORD * const dwHigh16,DWORD * const dwLow32);
/*
FUNCTION: Lan_InitializeTx
Prepares the LAN9118 for transmission of packets
must be called before
Lan_StartTx
Lan_SendTestPacket
Lan_SendPacketPIO
Lan_CompleteTx
*/
void Lan_InitializeTx(PLAN9118_DATA const pLan9118Data);
/*
FUNCTION: Lan_StartTx
Writes the initial 2 dwords to the tx data fifo
Must first call Lan_InitializeTx
*/
void Lan_StartTx(const LAN9118_DATA * const pLan9118Data, const DWORD dwTxCmdA, const DWORD dwTxCmdB);
/*
FUNCTION: Lan_SendTestPacket
Sends a dummy packet out on the ethernet line.
Must first call Lan_InitializeTx
*/
void Lan_SendTestPacket(CPCLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_SendPacketPIO
Sends a specified packet out on the ethernet line.
Must first call Lan_InitializeTx
WARNING: wPacketTag must not be 0. Zero is reserved.
*/
void Lan_SendPacketPIO(CPCLAN9118_DATA pLan9118Data, const WORD wPacketTag, const WORD wPacketLength, BYTE * pbPacketData);
/*
FUNCTION: Lan_CompleteTx
Gets the Status DWORD of a previous transmission from the TX status FIFO
If the TX Status FIFO is empty as indicated by TX_FIFO_INF then this
function will return 0
*/
DWORD Lan_CompleteTx(CPCLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_GetTxDataFreeSpace
Gets the free space available in the TX fifo
*/
DWORD Lan_GetTxDataFreeSpace(CPCLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_GetTxStatusCount
Gets the number of TX completion status' available on the TX_STATUS_FIFO
These can be read from Lan_CompleteTx
*/
DWORD Lan_GetTxStatusCount(CPCLAN9118_DATA pLan9118Data);
/*
FUNCTION: Lan_InitializeRx
Prepares the LAN9118 for reception of packets
Must be called After Lan_InitializeInterrupts
*/
void Lan_InitializeRx(CPCLAN9118_DATA pLan9118Data, const DWORD dwRxCfg, const DWORD dw);
/*
FUNCTION: Lan_PopRxStatus
If an Rx Status DWORD is available it will return it.
*/
DWORD Lan_PopRxStatus(CPCLAN9118_DATA pLan9118Data);
BOOLEAN Lan_AutoNegotiate(const LAN9118_DATA * const pLan9118Data);
BOOLEAN Phy_Reset(const LAN9118_DATA * const pLan9118Data);
DWORD Phy_LBT_GetTxStatus(const LAN9118_DATA * const pLan9118Data);
DWORD Phy_LBT_GetRxStatus(const LAN9118_DATA * const pLan9118Data);
BOOLEAN Phy_CheckLoopBackPacket(LAN9118_DATA * const pLan9118Data);
BOOLEAN Phy_LoopBackTest(LAN9118_DATA * const pLan9118Data);
/*
****************************************************************************
****************************************************************************
* TX/RX FIFO Port Register (Direct Address)
* Offset (from Base Address)
* and bit definitions
****************************************************************************
****************************************************************************
*/
#define RX_DATA_FIFO_PORT (0x00UL)
#define TX_DATA_FIFO_PORT (0x20UL)
#define TX_CMD_A_INT_ON_COMP_ (0x80000000UL)
#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000UL)
#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000UL)
#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000UL)
#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000UL)
#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000UL)
#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000UL)
#define TX_CMD_A_INT_LAST_SEG_ (0x00001000UL)
#define TX_CMD_A_BUF_SIZE_ (0x000007FFUL)
#define TX_CMD_B_PKT_TAG_ (0xFFFF0000UL)
#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000UL)
#define TX_CMD_B_DISABLE_PADDING_ (0x00001000UL)
#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FFUL)
/*** (nw) suspect these are wrong, try V1.2 addresses
#define RX_STSTUS_FIFO_PORT (0x3CUL)
// NOTE: the status definitions in lan.h so that we can
// develop SW based on 12X status format
#define RX_FIFO_PEEK (0x40UL)
#define TX_STATUS_FIFO_PORT (0x44UL)
#define TX_FIFO_PEEK (0x48UL)
***/
#define RX_STATUS_FIFO_PORT (0x00000040UL)
#define RX_STS_ES (0x00008000UL)
#define RX_STS_LENGTH_ERR (0x00001000UL)
#define RX_STS_MULTICAST (0x00000400UL)
#define RX_STS_FRAME_TYPE (0x00000020UL)
#define RX_FIFO_PEEK (0x00000044UL)
#define TX_STATUS_FIFO_PORT (0x00000048UL)
#define TX_FIFO_PEEK (0x0000004CUL)
/*
****************************************************************************
****************************************************************************
* Slave Interface Module Control and Status Register (Direct Address)
* Offset (from Base Address)
* and bit definitions
****************************************************************************
****************************************************************************
*/
#define ID_REV (0x50UL)
#define ID_REV_CHIP_ID_ (0xFFFF0000UL) // RO default 0x012X
#define ID_REV_REV_ID_ (0x0000FFFFUL) // RO
#define INT_CFG (0x54UL)
#define INT_CFG_INT_DEAS_ (0xFF000000UL) // R/W
#define INT_CFG_IRQ_INT_ (0x00001000UL) // RO
#define INT_CFG_IRQ_EN_ (0x00000100UL) // R/W
#define INT_CFG_IRQ_POL_ (0x00000010UL) // R/W Not Affected by SW Reset
#define INT_CFG_IRQ_TYPE_ (0x00000001UL) // R/W Not Affected by SW Reset
#define INT_CFG_IRQ_RESERVED_ (0x00FFCEEEUL) //Reserved bits mask
#define INT_STS (0x58UL)
#define INT_STS_SW_INT_ (0x80000000UL) // R/WC
#define INT_STS_TXSTOP_INT_ (0x02000000UL) // R/WC
#define INT_STS_RXSTOP_INT_ (0x01000000UL) // R/WC
#define INT_STS_RXDFH_INT_ (0x00800000UL) // R/WC
#define INT_STS_RXDF_INT_ (0x00400000UL) // R/WC
#define INT_STS_TX_IOC_ (0x00200000UL) // R/WC
#define INT_STS_RXD_INT_ (0x00100000UL) // R/WC
#define INT_STS_GPT_INT_ (0x00080000UL) // R/WC
#define INT_STS_PHY_INT_ (0x00040000UL) // RO
#define INT_STS_PME_INT_ (0x00020000UL) // R/WC
#define INT_STS_TXSO_ (0x00010000UL) // R/WC
#define INT_STS_RWT_ (0x00008000UL) // R/WC
#define INT_STS_RXE_ (0x00004000UL) // R/WC
#define INT_STS_TXE_ (0x00002000UL) // R/WC
#define INT_STS_ERX_ (0x00001000UL) // R/WC
#define INT_STS_TDFU_ (0x00000800UL) // R/WC
#define INT_STS_TDFO_ (0x00000400UL) // R/WC
#define INT_STS_TDFA_ (0x00000200UL) // R/WC
#define INT_STS_TSFF_ (0x00000100UL) // R/WC
#define INT_STS_TSFL_ (0x00000080UL) // R/WC
#define INT_STS_RDFO_ (0x00000040UL) // R/WC
#define INT_STS_RDFL_ (0x00000020UL) // R/WC
#define INT_STS_RSFF_ (0x00000010UL) // R/WC
#define INT_STS_RSFL_ (0x00000008UL) // R/WC
#define INT_STS_GPIO2_INT_ (0x00000004UL) // R/WC
#define INT_STS_GPIO1_INT_ (0x00000002UL) // R/WC
#define INT_STS_GPIO0_INT_ (0x00000001UL) // R/WC
#define INT_EN (0x5CUL)
#define INT_EN_SW_INT_EN_ (0x80000000UL) // R/W
#define INT_EN_TXSTOP_INT_EN_ (0x02000000UL) // R/W
#define INT_EN_RXSTOP_INT_EN_ (0x01000000UL) // R/W
#define INT_EN_RXDFH_INT_EN_ (0x00800000UL) // R/W
#define INT_EN_RXDF_INT_EN_ (0x00400000UL) // R/W
#define INT_EN_TIOC_INT_EN_ (0x00200000UL) // R/W
#define INT_EN_RXD_INT_EN_ (0x00100000UL) // R/W
#define INT_EN_GPT_INT_EN_ (0x00080000UL) // R/W
#define INT_EN_PHY_INT_EN_ (0x00040000UL) // R/W
#define INT_EN_PME_INT_EN_ (0x00020000UL) // R/W
#define INT_EN_TXSO_EN_ (0x00010000UL) // R/W
#define INT_EN_RWT_EN_ (0x00008000UL) // R/W
#define INT_EN_RXE_EN_ (0x00004000UL) // R/W
#define INT_EN_TXE_EN_ (0x00002000UL) // R/W
#define INT_EN_ERX_EN_ (0x00001000UL) // R/W
#define INT_EN_TDFU_EN_ (0x00000800UL) // R/W
#define INT_EN_TDFO_EN_ (0x00000400UL) // R/W
#define INT_EN_TDFA_EN_ (0x00000200UL) // R/W
#define INT_EN_TSFF_EN_ (0x00000100UL) // R/W
#define INT_EN_TSFL_EN_ (0x00000080UL) // R/W
#define INT_EN_RDFO_EN_ (0x00000040UL) // R/W
#define INT_EN_RDFL_EN_ (0x00000020UL) // R/W
#define INT_EN_RSFF_EN_ (0x00000010UL) // R/W
#define INT_EN_RSFL_EN_ (0x00000008UL) // R/W
#define INT_EN_GPIO2_INT_ (0x00000004UL) // R/W
#define INT_EN_GPIO1_INT_ (0x00000002UL) // R/W
#define INT_EN_GPIO0_INT_ (0x00000001UL) // R/W
#define DMA_CFG (0x60UL)
#define DMA_CFG_DRQ1_DEAS_ (0xFF000000UL) // R/W
#define DMA_CFG_DMA1_MODE_ (0x00200000UL) // R/W
#define DMA_CFG_DMA1_FUNC_ (0x00180000UL) // R/W
#define DMA_CFG_DMA1_FUNC_DISABLED_ (0x000000000UL) // R/W
#define DMA_CFG_DMA1_FUNC_TX_DMA_ (0x000800000UL) // R/W
#define DMA_CFG_DMA1_FUNC_RX_DMA_ (0x001000000UL) // R/W
#define DMA_CFG_DRQ1_BUFF_ (0x00040000UL) // R/W
#define DMA_CFG_DRQ1_POL_ (0x00020000UL) // R/W
#define DMA_CFG_DAK1_POL_ (0x00010000UL) // R/W
#define DMA_CFG_DRQ0_DEAS_ (0x0000FF00UL) // R/W
#define DMA_CFG_DMA0_MODE_ (0x00000020UL) // R/W
#define DMA_CFG_DMA0_FUNC_ (0x00000018UL) // R/W
#define DMA_CFG_DMA0_FUNC_FIFO_SEL_ (0x000000000UL) // R/W
#define DMA_CFG_DMA0_FUNC_TX_DMA_ (0x000000008UL) // R/W
#define DMA_CFG_DMA0_FUNC_RX_DMA_ (0x000000010UL) // R/W
#define DMA_CFG_DRQ0_BUFF_ (0x00000004UL) // R/W
#define DMA_CFG_DRQ0_POL_ (0x00000002UL) // R/W
#define DMA_CFG_DAK0_POL_ (0x00000001UL) // R/W
#define BYTE_TEST (0x64UL) // RO default 0x87654321
#define FIFO_INT (0x68UL)
#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000UL) // R/W
#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000UL) // R/W
#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00UL) // R/W
#define FIFO_INT_RX_STS_LEVEL_ (0x000000FFUL) // R/W
#define RX_CFG (0x6CUL)
#define RX_CFG_RX_END_ALGN_ (0xC0000000UL) // R/W
#define RX_CFG_RX_END_ALGN4_ (0x00000000UL) // R/W
#define RX_CFG_RX_END_ALGN16_ (0x40000000UL) // R/W
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