📄 i2c.lis
字号:
00FE 27FE sbrs R2,7
0100 FCCF rjmp L38
0102 .dbline 57
0102 .dbline 57
0102 .dbline 59
0102 ;
0102 ; if((TWSR&0xf8)!=MT_SLA_ACK) return 1;
0102 80917100 lds R24,113
0106 887F andi R24,248
0108 8831 cpi R24,24
010A 11F0 breq L41
010C .dbline 59
010C 01E0 ldi R16,1
010E 43C0 xjmp L32
0110 L41:
0110 .dbline 61
0110 ;
0110 ; write8bit(romadress);
0110 .dbline 61
0110 00937300 sts 115,R16
0114 .dbline 61
0114 84E8 ldi R24,132
0116 80937400 sts 116,R24
011A .dbline 61
011A .dbline 61
011A .dbline 62
011A L43:
011A .dbline 62
011A L44:
011A .dbline 62
011A ; wait;
011A 20907400 lds R2,116
011E 27FE sbrs R2,7
0120 FCCF rjmp L43
0122 .dbline 62
0122 .dbline 62
0122 .dbline 64
0122 ;
0122 ; if ((TWSR&0xf8)!=MT_DATA_ACK) return 1;
0122 80917100 lds R24,113
0126 887F andi R24,248
0128 8832 cpi R24,40
012A 11F0 breq L46
012C .dbline 64
012C 01E0 ldi R16,1
012E 33C0 xjmp L32
0130 L46:
0130 .dbline 66
0130 ;
0130 ; start;
0130 84EA ldi R24,164
0132 80937400 sts 116,R24
0136 .dbline 67
0136 L48:
0136 .dbline 67
0136 L49:
0136 .dbline 67
0136 ; wait;
0136 20907400 lds R2,116
013A 27FE sbrs R2,7
013C FCCF rjmp L48
013E .dbline 67
013E .dbline 67
013E .dbline 68
013E ; if ((TWSR&0xf8)!=restart) return 1;
013E 80917100 lds R24,113
0142 887F andi R24,248
0144 8031 cpi R24,16
0146 11F0 breq L51
0148 .dbline 68
0148 01E0 ldi R16,1
014A 25C0 xjmp L32
014C L51:
014C .dbline 70
014C ;
014C ; write8bit(rd_device_adress);
014C .dbline 70
014C 81EA ldi R24,161
014E 80937300 sts 115,R24
0152 .dbline 70
0152 .dbline 70
0152 84E8 ldi R24,132
0154 80937400 sts 116,R24
0158 .dbline 70
0158 .dbline 70
0158 .dbline 71
0158 L53:
0158 .dbline 71
0158 L54:
0158 .dbline 71
0158 ; wait;
0158 20907400 lds R2,116
015C 27FE sbrs R2,7
015E FCCF rjmp L53
0160 .dbline 71
0160 .dbline 71
0160 .dbline 72
0160 ; if((TWSR&0xf8)!=MR_SLA_ACK) return 1;
0160 80917100 lds R24,113
0164 887F andi R24,248
0166 8034 cpi R24,64
0168 11F0 breq L56
016A .dbline 72
016A 01E0 ldi R16,1
016C 14C0 xjmp L32
016E L56:
016E .dbline 74
016E ;
016E ; Twi;
016E 84E8 ldi R24,132
0170 80937400 sts 116,R24
0174 .dbline 75
0174 L58:
0174 .dbline 75
0174 L59:
0174 .dbline 75
0174 ; wait;
0174 20907400 lds R2,116
0178 27FE sbrs R2,7
017A FCCF rjmp L58
017C .dbline 75
017C .dbline 75
017C .dbline 77
017C ;
017C ; if((TWSR&0xf8)!=MR_DATA_NOACK) return 1;
017C 80917100 lds R24,113
0180 887F andi R24,248
0182 8835 cpi R24,88
0184 11F0 breq L61
0186 .dbline 77
0186 01E0 ldi R16,1
0188 06C0 xjmp L32
018A L61:
018A .dbline 79
018A ;
018A ; temp=TWDR;
018A 40917300 lds R20,115
018E .dbline 80
018E ; stop;
018E 84E9 ldi R24,148
0190 80937400 sts 116,R24
0194 .dbline 81
0194 ; return temp;
0194 042F mov R16,R20
0196 .dbline -2
0196 L32:
0196 0E940000 xcall pop_gset1
019A .dbline 0 ; func end
019A 0895 ret
019C .dbsym r temp 20 c
019C .dbsym r romadress 16 c
019C .dbend
019C .dbfunc e twi_init _twi_init fV
.even
019C _twi_init::
019C .dbline -1
019C .dbline 84
019C ; }
019C ; void twi_init(void)
019C ; {
019C .dbline 85
019C ; DDRD=0XFF;
019C 8FEF ldi R24,255
019E 81BB out 0x11,R24
01A0 .dbline 86
01A0 ; PORTD=0Xff;
01A0 82BB out 0x12,R24
01A2 .dbline 87
01A2 ; TWCR= 0X00; //disable twi
01A2 2224 clr R2
01A4 20927400 sts 116,R2
01A8 .dbline 88
01A8 ; TWBR= 0x64; //set bit rate
01A8 84E6 ldi R24,100
01AA 80937000 sts 112,R24
01AE .dbline 89
01AE ; TWSR= 0x00; //set prescale
01AE 20927100 sts 113,R2
01B2 .dbline 90
01B2 ; TWAR= 0x00; //set slave address
01B2 20927200 sts 114,R2
01B6 .dbline 91
01B6 ; TWCR= 0x04; //enable twi
01B6 84E0 ldi R24,4
01B8 80937400 sts 116,R24
01BC .dbline -2
01BC L63:
01BC .dbline 0 ; func end
01BC 0895 ret
01BE .dbend
01BE .dbfunc e main _main fV
01BE ; data -> R20
01BE ; adress -> R22
.even
01BE _main::
01BE .dbline -1
01BE .dbline 95
01BE ; }
01BE ;
01BE ; void main(void)
01BE ; {
01BE .dbline 96
01BE ; unsigned char data=0x00;
01BE 4427 clr R20
01C0 .dbline 97
01C0 ; unsigned char adress=0x00;
01C0 6627 clr R22
01C2 .dbline 98
01C2 ; twi_init();
01C2 ECDF xcall _twi_init
01C4 1DC0 xjmp L66
01C6 L65:
01C6 .dbline 106
01C6 ;
01C6 ;
01C6 ;
01C6 ;
01C6 ;
01C6 ;
01C6 ; while(1)
01C6 ; {
01C6 .dbline 107
01C6 ; for(data=0x00,adress=0x00;adress<255;data++,adress++)
01C6 4427 clr R20
01C8 6627 clr R22
01CA 18C0 xjmp L71
01CC L68:
01CC .dbline 108
01CC ; {i2cwrite(data,adress);
01CC .dbline 108
01CC 262F mov R18,R22
01CE 042F mov R16,R20
01D0 31DF xcall _i2cwrite
01D2 .dbline 109
01D2 ; DDRB=0xFF;
01D2 8FEF ldi R24,255
01D4 87BB out 0x17,R24
01D6 .dbline 110
01D6 ; if(data==i2cread(adress))
01D6 062F mov R16,R22
01D8 7ADF xcall _i2cread
01DA 4017 cp R20,R16
01DC 51F4 brne L72
01DE .dbline 111
01DE ; {delay_ms(5);
01DE .dbline 111
01DE 05E0 ldi R16,5
01E0 10E0 ldi R17,0
01E2 19DF xcall _delay_ms
01E4 .dbline 112
01E4 ; PORTB=i2cread(adress);
01E4 062F mov R16,R22
01E6 73DF xcall _i2cread
01E8 08BB out 0x18,R16
01EA .dbline 113
01EA ; delay_ms(50);}
01EA 02E3 ldi R16,50
01EC 10E0 ldi R17,0
01EE 13DF xcall _delay_ms
01F0 .dbline 113
01F0 03C0 xjmp L73
01F2 L72:
01F2 .dbline 115
01F2 ; else
01F2 ; {PORTB=0xff;
01F2 .dbline 115
01F2 8FEF ldi R24,255
01F4 88BB out 0x18,R24
01F6 L74:
01F6 .dbline 116
01F6 L75:
01F6 .dbline 116
01F6 FFCF xjmp L74
01F8 X0:
01F8 .dbline 116
01F8 ; while(1);}
01F8 L73:
01F8 .dbline 117
01F8 L69:
01F8 .dbline 107
01F8 4395 inc R20
01FA 6395 inc R22
01FC L71:
01FC .dbline 107
01FC 6F3F cpi R22,255
01FE 30F3 brlo L68
0200 .dbline 119
0200 L66:
0200 .dbline 105
0200 E2CF xjmp L65
0202 X1:
0202 .dbline -2
0202 L64:
0202 .dbline 0 ; func end
0202 0895 ret
0204 .dbsym r data 20 c
0204 .dbsym r adress 22 c
0204 .dbend
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