i2c.s

使用AVR做的IIC主模式下的程序

	.module i2c.c
	.area text(rom, con, rel)
	.dbfile E:\mine\i2c\i2c.c
	.dbfunc e delay_1ms _delay_1ms fV
;              i -> R16,R17
	.even
_delay_1ms::
	.dbline -1
	.dbline 17
; #include<iom128v.h>
; #include<iom128v.h>
; #define START 0x08
; #define restart 0x10
; #define MT_SLA_ACK 0x18
; #define MT_DATA_ACK 0x28
; #define MR_SLA_ACK  0x40 
; #define MR_DATA_NOACK 0x58  
; #define wr_device_adress 0xa0;
; #define rd_device_adress 0xa1;
; #define start TWCR=(1<<TWINT)|(1<<TWEN)|(1<<TWSTA)
; #define wait { while(!(TWCR&(1<<TWINT)));}
; #define stop TWCR=(1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
; #define write8bit(c){TWDR=c;TWCR=(1<<TWINT)|(1<<TWEN);}
; #define Twi           (TWCR=(1<<TWINT)|(1<<TWEN)) 
; void delay_1ms(void)
; {
	.dbline 19
	clr R16
	clr R17
	xjmp L5
L2:
	.dbline 19
L3:
	.dbline 19
	subi R16,255  ; offset = 1
	sbci R17,255
L5:
	.dbline 19
; unsigned int i;
; for(i=0;i<=8000;i++);
	ldi R24,8000
	ldi R25,31
	cp R24,R16
	cpc R25,R17
	brsh L2
	.dbline -2
L1:
	.dbline 0 ; func end
	ret
	.dbsym r i 16 i
	.dbend
	.dbfunc e delay_ms _delay_ms fV
;              i -> R20,R21
;              n -> R22,R23
	.even
_delay_ms::
	xcall push_gset2
	movw R22,R16
	.dbline -1
	.dbline 22
; }
; void delay_ms(unsigned int n)
; {
	.dbline 24
; unsigned int i;
; for(i=0;i<n;i++)
	clr R20
	clr R21
	xjmp L10
L7:
	.dbline 25
	xcall _delay_1ms
L8:
	.dbline 24
	subi R20,255  ; offset = 1
	sbci R21,255
L10:
	.dbline 24
	cp R20,R22
	cpc R21,R23
	brlo L7
	.dbline -2
L6:
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r i 20 i
	.dbsym r n 22 i
	.dbend
	.dbfunc e i2cwrite _i2cwrite fc
;      romadress -> R22
;           data -> R20
	.even
_i2cwrite::
	xcall push_gset2
	mov R22,R18
	mov R20,R16
	.dbline -1
	.dbline 28
; delay_1ms();
; }
; unsigned char i2cwrite(unsigned char data,unsigned char romadress)
; {
	.dbline 29
; start;
	ldi R24,164
	sts 116,R24
	.dbline 30
L12:
	.dbline 30
L13:
	.dbline 30
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L12
	.dbline 30
	.dbline 30
	.dbline 32
; 
; if((TWSR&0xf8)!=START) return 1;
	lds R24,113
	andi R24,248
	cpi R24,8
	breq L15
	.dbline 32
	ldi R16,1
	xjmp L11
L15:
	.dbline 34
; 
; write8bit(wr_device_adress);
	.dbline 34
	ldi R24,160
	sts 115,R24
	.dbline 34
	.dbline 34
	ldi R24,132
	sts 116,R24
	.dbline 34
	.dbline 34
	.dbline 35
L17:
	.dbline 35
L18:
	.dbline 35
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L17
	.dbline 35
	.dbline 35
	.dbline 36
; if((TWSR&0xf8)!=MT_SLA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,24
	breq L20
	.dbline 36
	ldi R16,1
	xjmp L11
L20:
	.dbline 37
; write8bit(romadress)
	.dbline 37
	sts 115,R22
	.dbline 37
	ldi R24,132
	sts 116,R24
	.dbline 37
	.dbline 38
L22:
	.dbline 38
L23:
	.dbline 38
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L22
	.dbline 38
	.dbline 38
	.dbline 39
; if((TWSR&0xf8)!=MT_DATA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,40
	breq L25
	.dbline 39
	ldi R16,1
	xjmp L11
L25:
	.dbline 40
; write8bit(data);
	.dbline 40
	sts 115,R20
	.dbline 40
	ldi R24,132
	sts 116,R24
	.dbline 40
	.dbline 40
	.dbline 41
L27:
	.dbline 41
L28:
	.dbline 41
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L27
	.dbline 41
	.dbline 41
	.dbline 42
; if((TWSR&0xf8)!=MT_DATA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,40
	breq L30
	.dbline 42
	ldi R16,1
	xjmp L11
L30:
	.dbline 43
; stop;
	ldi R24,148
	sts 116,R24
	.dbline 44
; delay_ms(10);
	ldi R16,10
	ldi R17,0
	xcall _delay_ms
	.dbline 45
; return 0;
	clr R16
	.dbline -2
L11:
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r romadress 22 c
	.dbsym r data 20 c
	.dbend
	.dbfunc e i2cread _i2cread fc
;           temp -> R20
;      romadress -> R16
	.even
_i2cread::
	xcall push_gset1
	.dbline -1
	.dbline 48
; }
; unsigned char i2cread(unsigned char romadress)
; {unsigned char temp;
	.dbline 49
; start;
	ldi R24,164
	sts 116,R24
	.dbline 50
L33:
	.dbline 50
L34:
	.dbline 50
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L33
	.dbline 50
	.dbline 50
	.dbline 52
; 
; if((TWSR&0xf8)!=START) 
	lds R24,113
	andi R24,248
	cpi R24,8
	breq L36
	.dbline 54
; 
; return 1;
	ldi R16,1
	xjmp L32
L36:
	.dbline 56
; 
; write8bit(wr_device_adress);
	.dbline 56
	ldi R24,160
	sts 115,R24
	.dbline 56
	.dbline 56
	ldi R24,132
	sts 116,R24
	.dbline 56
	.dbline 56
	.dbline 57
L38:
	.dbline 57
L39:
	.dbline 57
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L38
	.dbline 57
	.dbline 57
	.dbline 59
; 
; if((TWSR&0xf8)!=MT_SLA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,24
	breq L41
	.dbline 59
	ldi R16,1
	xjmp L32
L41:
	.dbline 61
; 
; write8bit(romadress);
	.dbline 61
	sts 115,R16
	.dbline 61
	ldi R24,132
	sts 116,R24
	.dbline 61
	.dbline 61
	.dbline 62
L43:
	.dbline 62
L44:
	.dbline 62
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L43
	.dbline 62
	.dbline 62
	.dbline 64
; 
; if ((TWSR&0xf8)!=MT_DATA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,40
	breq L46
	.dbline 64
	ldi R16,1
	xjmp L32
L46:
	.dbline 66
; 
; start;
	ldi R24,164
	sts 116,R24
	.dbline 67
L48:
	.dbline 67
L49:
	.dbline 67
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L48
	.dbline 67
	.dbline 67
	.dbline 68
; if ((TWSR&0xf8)!=restart) return 1;
	lds R24,113
	andi R24,248
	cpi R24,16
	breq L51
	.dbline 68
	ldi R16,1
	xjmp L32
L51:
	.dbline 70
; 
; write8bit(rd_device_adress);
	.dbline 70
	ldi R24,161
	sts 115,R24
	.dbline 70
	.dbline 70
	ldi R24,132
	sts 116,R24
	.dbline 70
	.dbline 70
	.dbline 71
L53:
	.dbline 71
L54:
	.dbline 71
; wait;
	lds R2,116
	sbrs R2,7
	rjmp L53
	.dbline 71
	.dbline 71
	.dbline 72
; if((TWSR&0xf8)!=MR_SLA_ACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,64
	breq L56
	.dbline 72
	ldi R16,1
	xjmp L32
L56:
	.dbline 74
; 
; Twi;
	ldi R24,132
	sts 116,R24
	.dbline 75
L58:
	.dbline 75
L59:
	.dbline 75
; wait;  
	lds R2,116
	sbrs R2,7
	rjmp L58
	.dbline 75
	.dbline 75
	.dbline 77
;  
; if((TWSR&0xf8)!=MR_DATA_NOACK) return 1;
	lds R24,113
	andi R24,248
	cpi R24,88
	breq L61
	.dbline 77
	ldi R16,1
	xjmp L32
L61:
	.dbline 79
;    
; temp=TWDR;     
	lds R20,115
	.dbline 80
; stop;
	ldi R24,148
	sts 116,R24
	.dbline 81
; return temp;
	mov R16,R20
	.dbline -2
L32:
	xcall pop_gset1
	.dbline 0 ; func end
	ret
	.dbsym r temp 20 c
	.dbsym r romadress 16 c
	.dbend
	.dbfunc e twi_init _twi_init fV
	.even
_twi_init::
	.dbline -1
	.dbline 84
; }
; void twi_init(void)
; {
	.dbline 85
; DDRD=0XFF;
	ldi R24,255
	out 0x11,R24
	.dbline 86
; PORTD=0Xff;
	out 0x12,R24
	.dbline 87
;  TWCR= 0X00; //disable twi
	clr R2
	sts 116,R2
	.dbline 88
;  TWBR= 0x64; //set bit rate
	ldi R24,100
	sts 112,R24
	.dbline 89
;  TWSR= 0x00; //set prescale
	sts 113,R2
	.dbline 90
;  TWAR= 0x00; //set slave address
	sts 114,R2
	.dbline 91
;  TWCR= 0x04; //enable twi
	ldi R24,4
	sts 116,R24
	.dbline -2
L63:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e main _main fV
;           data -> R20
;         adress -> R22
	.even
_main::
	.dbline -1
	.dbline 95
; }
; 
; void main(void)
; {
	.dbline 96
; unsigned char data=0x00;
	clr R20
	.dbline 97
; unsigned char adress=0x00;
	clr R22
	.dbline 98
; twi_init();
	xcall _twi_init
	xjmp L66
L65:
	.dbline 106
; 
; 
; 
; 
; 
; 
; while(1)
; {
	.dbline 107
; for(data=0x00,adress=0x00;adress<255;data++,adress++)
	clr R20
	clr R22
	xjmp L71
L68:
	.dbline 108
; {i2cwrite(data,adress);
	.dbline 108
	mov R18,R22
	mov R16,R20
	xcall _i2cwrite
	.dbline 109
; DDRB=0xFF;
	ldi R24,255
	out 0x17,R24
	.dbline 110
; if(data==i2cread(adress))
	mov R16,R22
	xcall _i2cread
	cp R20,R16
	brne L72
	.dbline 111
; {delay_ms(5);
	.dbline 111
	ldi R16,5
	ldi R17,0
	xcall _delay_ms
	.dbline 112
; PORTB=i2cread(adress);
	mov R16,R22
	xcall _i2cread
	out 0x18,R16
	.dbline 113
; delay_ms(50);}
	ldi R16,50
	ldi R17,0
	xcall _delay_ms
	.dbline 113
	xjmp L73
L72:
	.dbline 115
; else
; {PORTB=0xff;
	.dbline 115
	ldi R24,255
	out 0x18,R24
L74:
	.dbline 116
L75:
	.dbline 116
	xjmp L74
X0:
	.dbline 116
; while(1);}
L73:
	.dbline 117
L69:
	.dbline 107
	inc R20
	inc R22
L71:
	.dbline 107
	cpi R22,255
	brlo L68
	.dbline 119
L66:
	.dbline 105
	xjmp L65
X1:
	.dbline -2
L64:
	.dbline 0 ; func end
	ret
	.dbsym r data 20 c
	.dbsym r adress 22 c
	.dbend