📄 i2c.lst
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__text_start:
__start:
0046 EFCF LDI R28,0xFF
0047 E1D0 LDI R29,0x10
0048 BFCD OUT 0x3D,R28
0049 BFDE OUT 0x3E,R29
004A 51C0 SUBI R28,0x10
004B 40D0 SBCI R29,0
004C EA0A LDI R16,0xAA
004D 8308 STD Y+0,R16
004E 2400 CLR R0
004F E0E0 LDI R30,0
0050 E0F1 LDI R31,1
0051 E011 LDI R17,1
0052 30E0 CPI R30,0
0053 07F1 CPC R31,R17
0054 F011 BEQ 0x0057
0055 9201 ST R0,Z+
0056 CFFB RJMP 0x0052
0057 8300 STD Z+0,R16
0058 E8EC LDI R30,0x8C
0059 E0F0 LDI R31,0
005A E0A0 LDI R26,0
005B E0B1 LDI R27,1
005C E010 LDI R17,0
005D 38EC CPI R30,0x8C
005E 07F1 CPC R31,R17
005F F021 BEQ 0x0064
0060 95C8 LPM
0061 9631 ADIW R30,1
0062 920D ST R0,X+
0063 CFF9 RJMP 0x005D
0064 940E0146 CALL _main
_exit:
0066 CFFF RJMP _exit
FILE: E:\mine\i2c\i2c.c
(0001) #include<iom128v.h>
(0002) #include<iom128v.h>
(0003) #define START 0x08
(0004) #define restart 0x10
(0005) #define MT_SLA_ACK 0x18
(0006) #define MT_DATA_ACK 0x28
(0007) #define MR_SLA_ACK 0x40
(0008) #define MR_DATA_NOACK 0x58
(0009) #define wr_device_adress 0xa0;
(0010) #define rd_device_adress 0xa1;
(0011) #define start TWCR=(1<<TWINT)|(1<<TWEN)|(1<<TWSTA)
(0012) #define wait { while(!(TWCR&(1<<TWINT)));}
(0013) #define stop TWCR=(1<<TWINT)|(1<<TWEN)|(1<<TWSTO)
(0014) #define write8bit(c){TWDR=c;TWCR=(1<<TWINT)|(1<<TWEN);}
(0015) #define Twi (TWCR=(1<<TWINT)|(1<<TWEN))
(0016) void delay_1ms(void)
(0017) {
(0018) unsigned int i;
(0019) for(i=0;i<=8000;i++);
_delay_1ms:
i --> R16
0067 2700 CLR R16
0068 2711 CLR R17
0069 C002 RJMP 0x006C
006A 5F0F SUBI R16,0xFF
006B 4F1F SBCI R17,0xFF
006C E480 LDI R24,0x40
006D E19F LDI R25,0x1F
006E 1780 CP R24,R16
006F 0791 CPC R25,R17
0070 F7C8 BCC 0x006A
0071 9508 RET
_delay_ms:
i --> R20
n --> R22
0072 940E0172 CALL push_gset2
0074 01B8 MOVW R22,R16
(0020) }
(0021) void delay_ms(unsigned int n)
(0022) {
(0023) unsigned int i;
(0024) for(i=0;i<n;i++)
0075 2744 CLR R20
0076 2755 CLR R21
0077 C003 RJMP 0x007B
(0025) delay_1ms();
0078 DFEE RCALL _delay_1ms
0079 5F4F SUBI R20,0xFF
007A 4F5F SBCI R21,0xFF
007B 1746 CP R20,R22
007C 0757 CPC R21,R23
007D F3D0 BCS 0x0078
007E 940E0169 CALL pop_gset2
0080 9508 RET
_i2cwrite:
romadress --> R22
data --> R20
0081 940E0172 CALL push_gset2
0083 2F62 MOV R22,R18
0084 2F40 MOV R20,R16
(0026) }
(0027) unsigned char i2cwrite(unsigned char data,unsigned char romadress)
(0028) {
(0029) start;
0085 EA84 LDI R24,0xA4
0086 93800074 STS 0x74,R24
(0030) wait;
0088 90200074 LDS R2,0x74
008A FE27 SBRS R2,7
008B CFFC RJMP 0x0088
(0031)
(0032) if((TWSR&0xf8)!=START) return 1;
008C 91800071 LDS R24,0x71
008E 7F88 ANDI R24,0xF8
008F 3088 CPI R24,0x8
0090 F011 BEQ 0x0093
0091 E001 LDI R16,1
0092 C038 RJMP 0x00CB
(0033)
(0034) write8bit(wr_device_adress);
0093 EA80 LDI R24,0xA0
0094 93800073 STS 0x73,R24
0096 E884 LDI R24,0x84
0097 93800074 STS 0x74,R24
(0035) wait;
0099 90200074 LDS R2,0x74
009B FE27 SBRS R2,7
009C CFFC RJMP 0x0099
(0036) if((TWSR&0xf8)!=MT_SLA_ACK) return 1;
009D 91800071 LDS R24,0x71
009F 7F88 ANDI R24,0xF8
00A0 3188 CPI R24,0x18
00A1 F011 BEQ 0x00A4
00A2 E001 LDI R16,1
00A3 C027 RJMP 0x00CB
(0037) write8bit(romadress)
00A4 93600073 STS 0x73,R22
00A6 E884 LDI R24,0x84
00A7 93800074 STS 0x74,R24
(0038) wait;
00A9 90200074 LDS R2,0x74
00AB FE27 SBRS R2,7
00AC CFFC RJMP 0x00A9
(0039) if((TWSR&0xf8)!=MT_DATA_ACK) return 1;
00AD 91800071 LDS R24,0x71
00AF 7F88 ANDI R24,0xF8
00B0 3288 CPI R24,0x28
00B1 F011 BEQ 0x00B4
00B2 E001 LDI R16,1
00B3 C017 RJMP 0x00CB
(0040) write8bit(data);
00B4 93400073 STS 0x73,R20
00B6 E884 LDI R24,0x84
00B7 93800074 STS 0x74,R24
(0041) wait;
00B9 90200074 LDS R2,0x74
00BB FE27 SBRS R2,7
00BC CFFC RJMP 0x00B9
(0042) if((TWSR&0xf8)!=MT_DATA_ACK) return 1;
00BD 91800071 LDS R24,0x71
00BF 7F88 ANDI R24,0xF8
00C0 3288 CPI R24,0x28
00C1 F011 BEQ 0x00C4
00C2 E001 LDI R16,1
00C3 C007 RJMP 0x00CB
(0043) stop;
00C4 E984 LDI R24,0x94
00C5 93800074 STS 0x74,R24
(0044) delay_ms(10);
00C7 E00A LDI R16,0xA
00C8 E010 LDI R17,0
00C9 DFA8 RCALL _delay_ms
(0045) return 0;
00CA 2700 CLR R16
00CB 940E0169 CALL pop_gset2
00CD 9508 RET
_i2cread:
temp --> R20
romadress --> R16
00CE 940E0174 CALL push_gset1
(0046) }
(0047) unsigned char i2cread(unsigned char romadress)
(0048) {unsigned char temp;
(0049) start;
00D0 EA84 LDI R24,0xA4
00D1 93800074 STS 0x74,R24
(0050) wait;
00D3 90200074 LDS R2,0x74
00D5 FE27 SBRS R2,7
00D6 CFFC RJMP 0x00D3
(0051)
(0052) if((TWSR&0xf8)!=START)
00D7 91800071 LDS R24,0x71
00D9 7F88 ANDI R24,0xF8
00DA 3088 CPI R24,0x8
00DB F011 BEQ 0x00DE
(0053)
(0054) return 1;
00DC E001 LDI R16,1
00DD C054 RJMP 0x0132
(0055)
(0056) write8bit(wr_device_adress);
00DE EA80 LDI R24,0xA0
00DF 93800073 STS 0x73,R24
00E1 E884 LDI R24,0x84
00E2 93800074 STS 0x74,R24
(0057) wait;
00E4 90200074 LDS R2,0x74
00E6 FE27 SBRS R2,7
00E7 CFFC RJMP 0x00E4
(0058)
(0059) if((TWSR&0xf8)!=MT_SLA_ACK) return 1;
00E8 91800071 LDS R24,0x71
00EA 7F88 ANDI R24,0xF8
00EB 3188 CPI R24,0x18
00EC F011 BEQ 0x00EF
00ED E001 LDI R16,1
00EE C043 RJMP 0x0132
(0060)
(0061) write8bit(romadress);
00EF 93000073 STS 0x73,R16
00F1 E884 LDI R24,0x84
00F2 93800074 STS 0x74,R24
(0062) wait;
00F4 90200074 LDS R2,0x74
00F6 FE27 SBRS R2,7
00F7 CFFC RJMP 0x00F4
(0063)
(0064) if ((TWSR&0xf8)!=MT_DATA_ACK) return 1;
00F8 91800071 LDS R24,0x71
00FA 7F88 ANDI R24,0xF8
00FB 3288 CPI R24,0x28
00FC F011 BEQ 0x00FF
00FD E001 LDI R16,1
00FE C033 RJMP 0x0132
(0065)
(0066) start;
00FF EA84 LDI R24,0xA4
0100 93800074 STS 0x74,R24
(0067) wait;
0102 90200074 LDS R2,0x74
0104 FE27 SBRS R2,7
0105 CFFC RJMP 0x0102
(0068) if ((TWSR&0xf8)!=restart) return 1;
0106 91800071 LDS R24,0x71
0108 7F88 ANDI R24,0xF8
0109 3180 CPI R24,0x10
010A F011 BEQ 0x010D
010B E001 LDI R16,1
010C C025 RJMP 0x0132
(0069)
(0070) write8bit(rd_device_adress);
010D EA81 LDI R24,0xA1
010E 93800073 STS 0x73,R24
0110 E884 LDI R24,0x84
0111 93800074 STS 0x74,R24
(0071) wait;
0113 90200074 LDS R2,0x74
0115 FE27 SBRS R2,7
0116 CFFC RJMP 0x0113
(0072) if((TWSR&0xf8)!=MR_SLA_ACK) return 1;
0117 91800071 LDS R24,0x71
0119 7F88 ANDI R24,0xF8
011A 3480 CPI R24,0x40
011B F011 BEQ 0x011E
011C E001 LDI R16,1
011D C014 RJMP 0x0132
(0073)
(0074) Twi;
011E E884 LDI R24,0x84
011F 93800074 STS 0x74,R24
(0075) wait;
0121 90200074 LDS R2,0x74
0123 FE27 SBRS R2,7
0124 CFFC RJMP 0x0121
(0076)
(0077) if((TWSR&0xf8)!=MR_DATA_NOACK) return 1;
0125 91800071 LDS R24,0x71
0127 7F88 ANDI R24,0xF8
0128 3588 CPI R24,0x58
0129 F011 BEQ 0x012C
012A E001 LDI R16,1
012B C006 RJMP 0x0132
(0078)
(0079) temp=TWDR;
012C 91400073 LDS R20,0x73
(0080) stop;
012E E984 LDI R24,0x94
012F 93800074 STS 0x74,R24
(0081) return temp;
0131 2F04 MOV R16,R20
0132 940E0177 CALL pop_gset1
0134 9508 RET
(0082) }
(0083) void twi_init(void)
(0084) {
(0085) DDRD=0XFF;
_twi_init:
0135 EF8F LDI R24,0xFF
0136 BB81 OUT 0x11,R24
(0086) PORTD=0Xff;
0137 BB82 OUT 0x12,R24
(0087) TWCR= 0X00; //disable twi
0138 2422 CLR R2
0139 92200074 STS 0x74,R2
(0088) TWBR= 0x64; //set bit rate
013B E684 LDI R24,0x64
013C 93800070 STS 0x70,R24
(0089) TWSR= 0x00; //set prescale
013E 92200071 STS 0x71,R2
(0090) TWAR= 0x00; //set slave address
0140 92200072 STS 0x72,R2
(0091) TWCR= 0x04; //enable twi
0142 E084 LDI R24,4
0143 93800074 STS 0x74,R24
0145 9508 RET
(0092) }
(0093)
(0094) void main(void)
(0095) {
(0096) unsigned char data=0x00;
_main:
data --> R20
adress --> R22
0146 2744 CLR R20
(0097) unsigned char adress=0x00;
0147 2766 CLR R22
(0098) twi_init();
0148 DFEC RCALL _twi_init
0149 C01D RJMP 0x0167
(0099)
(0100)
(0101)
(0102)
(0103)
(0104)
(0105) while(1)
(0106) {
(0107) for(data=0x00,adress=0x00;adress<255;data++,adress++)
014A 2744 CLR R20
014B 2766 CLR R22
014C C018 RJMP 0x0165
(0108) {i2cwrite(data,adress);
014D 2F26 MOV R18,R22
014E 2F04 MOV R16,R20
014F DF31 RCALL _i2cwrite
(0109) DDRB=0xFF;
0150 EF8F LDI R24,0xFF
0151 BB87 OUT 0x17,R24
(0110) if(data==i2cread(adress))
0152 2F06 MOV R16,R22
0153 DF7A RCALL _i2cread
0154 1740 CP R20,R16
0155 F451 BNE 0x0160
(0111) {delay_ms(5);
0156 E005 LDI R16,5
0157 E010 LDI R17,0
0158 DF19 RCALL _delay_ms
(0112) PORTB=i2cread(adress);
0159 2F06 MOV R16,R22
015A DF73 RCALL _i2cread
015B BB08 OUT 0x18,R16
(0113) delay_ms(50);}
015C E302 LDI R16,0x32
015D E010 LDI R17,0
015E DF13 RCALL _delay_ms
015F C003 RJMP 0x0163
(0114) else
(0115) {PORTB=0xff;
0160 EF8F LDI R24,0xFF
0161 BB88 OUT 0x18,R24
(0116) while(1);}
FILE: <library>
0162 CFFF RJMP 0x0162
0163 9543 INC R20
0164 9563 INC R22
0165 3F6F CPI R22,0xFF
0166 F330 BCS 0x014D
0167 CFE2 RJMP 0x014A
0168 9508 RET
pop_gset2:
0169 E0E2 LDI R30,2
016A 940C0178 JMP pop
push_gset5:
016C 92FA ST R15,-Y
016D 92EA ST R14,-Y
push_gset4:
016E 92DA ST R13,-Y
016F 92CA ST R12,-Y
push_gset3:
0170 92BA ST R11,-Y
0171 92AA ST R10,-Y
push_gset2:
0172 937A ST R23,-Y
0173 936A ST R22,-Y
push_gset1:
0174 935A ST R21,-Y
0175 934A ST R20,-Y
0176 9508 RET
pop_gset1:
0177 E0E1 LDI R30,1
pop:
0178 9149 LD R20,Y+
0179 9159 LD R21,Y+
017A FDE0 SBRC R30,0
017B 9508 RET
017C 9169 LD R22,Y+
017D 9179 LD R23,Y+
017E FDE1 SBRC R30,1
017F 9508 RET
0180 90A9 LD R10,Y+
0181 90B9 LD R11,Y+
0182 FDE2 SBRC R30,2
0183 9508 RET
0184 90C9 LD R12,Y+
0185 90D9 LD R13,Y+
0186 FDE3 SBRC R30,3
0187 9508 RET
0188 90E9 LD R14,Y+
0189 90F9 LD R15,Y+
018A 9508 RET
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