sys_register.h

凌阳32位单片机开发的小游戏

	#define P_MIC_GAIN				(U32*)(ADCBASE + 0x00000004)
	#define P_MCLK_SETUP			(U32*)(ADCBASE + 0x00000008)
	#define P_SH_SETUP				(U32*)(ADCBASE + 0x0000000c)
	#define P_AM_CTRL1				(U32*)(ADCBASE + 0x00000010)
	#define P_AM_CTRL2				(U32*)(ADCBASE + 0x00000014)
	#define P_ADC_DATA				(U32*)(ADCBASE + 0x00000018)
	#define P_ASP_DATA				(U32*)(ADCBASE + 0x0000001c)
	#define P_MIC_DATA				(U32*)(ADCBASE + 0x00000020)
	#define P_ADC_TEST				(U32*)(ADCBASE + 0x00000024)

/**
 * USB device: 0x081B_0000 ~ 0x081B_FFFF
 */
#define USBDEVBASE				0x881B0000

/**
 * USB host: 0x081C_0000 ~ 0x081C_FFFF
 */
#define USBHOSTBASE				0x881C0000

/**
 * Reserved: 0x081D_0000 ~ 0x081D_FFFF
 */
 

/**
 * Reserved: 0x081E_0000 ~ 0x081E_FFFF
 */


/**
 * Reserved: 0x081F_0000 ~ 0x081F_FFFF
 */


/**
 * SFTCFG: 0x0820_0000 ~ 0x0820_FFFF
 */
#define SFTCFGBASE				0x88200000
	#define P_TFT_GPIO_OUT			(U32*)(SFTCFGBASE + 0x00000014)
	#define P_TFT_GPIO_OE			(U32*)(SFTCFGBASE + 0x00000018)	
	#define P_TFT_GPIO_IN			(U32*)(SFTCFGBASE + 0x00000064)
	#define P_ADC_GPIO_OE			(U32*)(SFTCFGBASE + 0x00000048)
	#define P_ADC_GPIO_AEN			(U32*)(SFTCFGBASE + 0x00000054)	
	#define P_ADC_GPIO_IN			(U32*)(SFTCFGBASE + 0x00000078)
	#define P_SYS_C2M_STBLENG    	(U32*)(SFTCFGBASE + 0x000000c0)

/**
 * CKG: 0x0821_0000 ~ 0x0821_FFFF
 */
#define CKGBASE					0x88210000
	#define P_CKG_CFG_APBDMA		(U32*)(CKGBASE + (22 << 2))		
	#define P_CKG_CFG_UART			(U32*)(CKGBASE + (23 << 2))
	#define P_CKG_CFG_TIMER0		(U32*)(CKGBASE + (27 << 2))
	#define P_CKG_CFG_TIMER1		(U32*)(CKGBASE + (28 << 2))
	#define P_CKG_CFG_TIMER2		(U32*)(CKGBASE + (29 << 2))
	#define P_CKG_CFG_TIMER3		(U32*)(CKGBASE + (30 << 2))
	#define P_CKG_CFG_TIMER4		(U32*)(CKGBASE + (31 << 2))
	#define P_CKG_CFG_TIMER5		(U32*)(CKGBASE + (32 << 2))
	#define P_CKG_CFG_WDOG			(U32*)(CKGBASE + (33 << 2))		
	#define P_CKG_CFG_RTC			(U32*)(CKGBASE + (34 << 2))	
	#define P_CKG_CFG_I2S			(U32*)(CKGBASE + (35 << 2))
	#define P_CKG_SEL_I2S			(U32*)(CKGBASE + (36 << 2))
	#define P_CKG_CFG_SPI			(U32*)(CKGBASE + (38 << 2))
	#define P_CKG_SEL_SPI			(U32*)(CKGBASE + (39 << 2))
	#define P_CKG_CFG_ADC			(U32*)(CKGBASE + (43 << 2))
	#define P_CKG_SEL_ADC			(U32*)(CKGBASE + (44 << 2))
	#define P_CKG_CFG_PLLA		    (U32*)(CKGBASE + (47 << 2))	// added by Bruce
	#define P_CKG_CFG_TMB			(U32*)(CKGBASE + (56 << 2))
	#define P_CKG_SEL_TIMER			(U32*)(CKGBASE + (57 << 2))
	#define P_CKG_STS_WDOG			(U32*)(CKGBASE + (58 << 2))
	#define P_CKG_CFG_SFT			(U32*)(CKGBASE + (63 << 2))	// added by Bruce
	
	#define P_CKG_SEL_CPU				(UV32*)(CKGBASE + 0x00000004)
	#define P_I2S_CONF					(UV32*)(CKGBASE + 0x0000008C) 
	#define P_PLLV_FREQUENCY			(UV32*)(CKGBASE + 0x000000B8)
	#define P_PLLAU_CONF				(UV32*)(CKGBASE + 0x000000BC)		

/**
 * MP4: 0x0822_0000 ~ 0x0822_FFFF
 */
#define MPEG4BASE			0x88220000

/////////////////////////////////////////////////////////////////////////////////
// MPEG Engine Register Definition 
/////////////////////////////////////////////////////////////////////////////////
	#define P_mjwidth_low	        (U32*)(MPEG4BASE + (0x0000<<2))
	#define P_mjwidth_high	        (U32*)(MPEG4BASE + (0x0001<<2))
	#define P_mjheight_low	        (U32*)(MPEG4BASE + (0x0002<<2))
	#define P_mjheight_high	        (U32*)(MPEG4BASE + (0x0003<<2))
	#define P_Mjhoffset_low	        (U32*)(MPEG4BASE + (0x0004<<2))
	#define P_Mjhoffset_high	    (U32*)(MPEG4BASE + (0x0005<<2))
	#define P_Mjvoffset_low	        (U32*)(MPEG4BASE + (0x0006<<2))
	#define P_Mjvoffset_high	    (U32*)(MPEG4BASE + (0x0007<<2))
	#define P_VlcOffaddr_low	    (U32*)(MPEG4BASE + (0x0008<<2))
	#define P_VlcOffaddr_mid	    (U32*)(MPEG4BASE + (0x0009<<2))
	#define P_VlcOffaddr_high	    (U32*)(MPEG4BASE + (0x000a<<2))
	#define P_tmbOffaddr_low	    (U32*)(MPEG4BASE + (0x0010<<2))
	#define P_tmbOffaddr_mid	    (U32*)(MPEG4BASE + (0x0011<<2))
	#define P_tmbOffaddr_high	    (U32*)(MPEG4BASE + (0x0012<<2))
	#define P_Yuvsel	            (U32*)(MPEG4BASE + (0x0013<<2))
	#define P_setting_reg0014	    (U32*)(MPEG4BASE + (0x0014<<2))
	#define P_setting_reg0015	    (U32*)(MPEG4BASE + (0x0015<<2))
	#define P_Hsf	                (U32*)(MPEG4BASE + (0x0016<<2))
	#define P_Vsf	                (U32*)(MPEG4BASE + (0x0017<<2))
	#define P_Gopval	            (U32*)(MPEG4BASE + (0x0018<<2))
	#define P_setting_reg0019	    (U32*)(MPEG4BASE + (0x0019<<2))
	#define P_Vardthr_low	        (U32*)(MPEG4BASE + (0x001a<<2))
	#define P_Vardthr_high	        (U32*)(MPEG4BASE + (0x001b<<2))
	#define P_iniavgact	            (U32*)(MPEG4BASE + (0x001c<<2))
	#define P_Avgactwei_low	        (U32*)(MPEG4BASE + (0x001e<<2))
	#define P_Avgactwei_high	    (U32*)(MPEG4BASE + (0x001f<<2))
	#define P_mjpgrst	            (U32*)(MPEG4BASE + (0x0020<<2))
	#define P_setting_reg0021	    (U32*)(MPEG4BASE + (0x0021<<2))
	#define P_iframe	            (U32*)(MPEG4BASE + (0x0022<<2))
	#define P_Thumb_ctrl	        (U32*)(MPEG4BASE + (0x0023<<2))
	#define P_memcsram_ctrl	        (U32*)(MPEG4BASE + (0x0024<<2))
	#define P_probemode	            (U32*)(MPEG4BASE + (0x0025<<2))
	#define P_Bist_ctrl_mpeg	    (U32*)(MPEG4BASE + (0x0026<<2))
	#define P_sofeof_ctrl	        (U32*)(MPEG4BASE + (0x0028<<2))
	#define P_Ifrme	                (U32*)(MPEG4BASE + (0x0029<<2))
	#define P_AVGact	            (U32*)(MPEG4BASE + (0x002a<<2))
	#define P_avgvard	            (U32*)(MPEG4BASE + (0x002b<<2))
	#define P_meBistFail	        (U32*)(MPEG4BASE + (0x002c<<2))
	#define P_mcBistFail	        (U32*)(MPEG4BASE + (0x002d<<2))
	#define P_BistFinish	        (U32*)(MPEG4BASE + (0x002e<<2))
	#define P_Hsfini	            (U32*)(MPEG4BASE + (0x0030<<2))
	#define P_Vsfini	            (U32*)(MPEG4BASE + (0x0031<<2))
	#define P_setting_reg0032	    (U32*)(MPEG4BASE + (0x0032<<2))
	#define P_McMehsfl	            (U32*)(MPEG4BASE + (0x0033<<2))
	#define P_Int_Mask	            (U32*)(MPEG4BASE + (0x0034<<2))
	#define P_Int_clr	            (U32*)(MPEG4BASE + (0x0035<<2))
	#define P_setting_reg0036	    (U32*)(MPEG4BASE + (0x0036<<2))
	#define P_Vlcbufasize_low	    (U32*)(MPEG4BASE + (0x0037<<2))
	#define P_Vlcbufasize_mid	    (U32*)(MPEG4BASE + (0x0038<<2))
	#define P_Vlcbufasize_high	    (U32*)(MPEG4BASE + (0x0039<<2))
	#define P_Vlcbufbsize_low	    (U32*)(MPEG4BASE + (0x003a<<2))
	#define P_Vlcbufbsize_mid	    (U32*)(MPEG4BASE + (0x003b<<2))
	#define P_Vlcbufbsize_high	    (U32*)(MPEG4BASE + (0x003c<<2))
	#define P_decmjwidth_low	    (U32*)(MPEG4BASE + (0x0040<<2))
	#define P_decmjwidth_high	    (U32*)(MPEG4BASE + (0x0041<<2))
	#define P_decmjheight_low	    (U32*)(MPEG4BASE + (0x0042<<2))
	#define P_decmjheight_high	    (U32*)(MPEG4BASE + (0x0043<<2))
	#define P_decVlcOffaddr_low	    (U32*)(MPEG4BASE + (0x0044<<2))
	#define P_decVlcOffaddr_mid	    (U32*)(MPEG4BASE + (0x0045<<2))
	#define P_decVlcOffaddr_high	(U32*)(MPEG4BASE + (0x0046<<2))
	#define P_lastmemaddr_low	    (U32*)(MPEG4BASE + (0x0047<<2))
	#define P_lastmemaddr_mid	    (U32*)(MPEG4BASE + (0x0048<<2))
	#define P_lastmemaddr_high	    (U32*)(MPEG4BASE + (0x0049<<2))
	#define P_Lastlength	        (U32*)(MPEG4BASE + (0x004a<<2))
	/////////////////////////////////////////////////////////////////////////////////
	// Texture Engine Register Definition
	/////////////////////////////////////////////////////////////////////////////////
	// reg0100 ~ reg013f for Qtable1
	// reg0140 ~ reg017f for Qtable2
	#define P_Qtable1_str	        (U32*)(MPEG4BASE + (0x0100<<2))
	#define P_Qtable1_end	        (U32*)(MPEG4BASE + (0x013f<<2))
	#define P_Qtable2_str	        (U32*)(MPEG4BASE + (0x0140<<2))
	#define P_Qtable2_end	        (U32*)(MPEG4BASE + (0x017f<<2))
	#define P_Noqtbl	            (U32*)(MPEG4BASE + (0x0180<<2))
	#define P_setting_reg0181	    (U32*)(MPEG4BASE + (0x0181<<2))
	#define P_QSramEn	            (U32*)(MPEG4BASE + (0x0182<<2))
	#define P_setting_reg0183	    (U32*)(MPEG4BASE + (0x0183<<2))
	#define P_JFIF	                (U32*)(MPEG4BASE + (0x0184<<2))
	#define P_setting_reg0185	    (U32*)(MPEG4BASE + (0x0185<<2))
	#define P_Vlcbit	            (U32*)(MPEG4BASE + (0x0186<<2))
	#define P_JFIFend	            (U32*)(MPEG4BASE + (0x0187<<2))
	#define P_Restartmcu_low	    (U32*)(MPEG4BASE + (0x0188<<2))
	#define P_Restartmcu_high	    (U32*)(MPEG4BASE + (0x0189<<2))
	#define P_IframeQscale	        (U32*)(MPEG4BASE + (0x0190<<2))
	#define P_PframeQscale	        (U32*)(MPEG4BASE + (0x0191<<2))
	#define P_MatchCnt	            (U32*)(MPEG4BASE + (0x0192<<2))
	#define P_MatchCode0	        (U32*)(MPEG4BASE + (0x0193<<2))
	#define P_MatchCode1	        (U32*)(MPEG4BASE + (0x0194<<2))
	#define P_MatchCode2	        (U32*)(MPEG4BASE + (0x0195<<2))
	#define P_MatchCode3	        (U32*)(MPEG4BASE + (0x0196<<2))
	#define P_Offset	            (U32*)(MPEG4BASE + (0x0197<<2))
	#define P_VOPTimeIncMode	    (U32*)(MPEG4BASE + (0x0198<<2))
	#define P_MSCnt	                (U32*)(MPEG4BASE + (0x0199<<2))
	#define P_MSPlus_ctrl	        (U32*)(MPEG4BASE + (0x019a<<2))
	#define P_VOPTimeIncRes_low	    (U32*)(MPEG4BASE + (0x01a0<<2))
	#define P_VOPTimeIncRes_high	(U32*)(MPEG4BASE + (0x01a1<<2))
	#define P_VOPTimeInc_low	    (U32*)(MPEG4BASE + (0x01a2<<2))
	#define P_VOPTimeInc_high	    (U32*)(MPEG4BASE + (0x01a3<<2))
	#define P_VOPTimeIncLen	        (U32*)(MPEG4BASE + (0x01a4<<2))
	#define P_React_low	            (U32*)(MPEG4BASE + (0x01a6<<2))
	#define P_React_high	        (U32*)(MPEG4BASE + (0x01a7<<2))
	#define P_D0_Iframe_low	        (U32*)(MPEG4BASE + (0x01a8<<2))
	#define P_D0_Iframe_high	    (U32*)(MPEG4BASE + (0x01a9<<2))
	#define P_PreIframeMBByte_low	(U32*)(MPEG4BASE + (0x01aa<<2))
	#define P_PreIframeMBByte_high	(U32*)(MPEG4BASE + (0x01ab<<2))
	#define P_PrePframeMBByte_low	(U32*)(MPEG4BASE + (0x01ac<<2))
	#define P_PrePframeMBByte_high	(U32*)(MPEG4BASE + (0x01ad<<2))
	#define P_QscaleUpperB	        (U32*)(MPEG4BASE + (0x01ae<<2))
	#define P_QscaleLowerB	        (U32*)(MPEG4BASE + (0x01af<<2))
	#define P_D0_Pframe_low	        (U32*)(MPEG4BASE + (0x01b0<<2))
	#define P_D0_Pframe_high	    (U32*)(MPEG4BASE + (0x01b1<<2))
	#define P_VLCSize_low	        (U32*)(MPEG4BASE + (0x01b2<<2))
	#define P_VLCSize_mid	        (U32*)(MPEG4BASE + (0x01b3<<2))
	#define P_VLCSize_high	        (U32*)(MPEG4BASE + (0x01b4<<2))
	#define P_Qsum_low	            (U32*)(MPEG4BASE + (0x01b5<<2))
	#define P_Qsum_high	            (U32*)(MPEG4BASE + (0x01b6<<2))
	#define P_SRAM_CS_N	            (U32*)(MPEG4BASE + (0x01be<<2))
	#define P_auto_rst_dec	        (U32*)(MPEG4BASE + (0x01bf<<2))
	#define P_SRAM_test_ctrl	    (U32*)(MPEG4BASE + (0x01e0<<2))
	#define P_Tselect	            (U32*)(MPEG4BASE + (0x01e1<<2))
	#define P_Bist_ctrl_jpeg	    (U32*)(MPEG4BASE + (0x01e2<<2))
	#define P_jpegBistFail	        (U32*)(MPEG4BASE + (0x01e3<<2))
	#define P_Blockend	            (U32*)(MPEG4BASE + (0x01e4<<2))
	#define P_DeHuffmanen	        (U32*)(MPEG4BASE + (0x01e6<<2))
	#define P_DeHuffmanrdy	        (U32*)(MPEG4BASE + (0x01e7<<2))
	#define P_Vlddata_low	        (U32*)(MPEG4BASE + (0x01e8<<2))
	#define P_Vlddata_high	        (U32*)(MPEG4BASE + (0x01e9<<2))
	#define P_VideoRstMode	        (U32*)(MPEG4BASE + (0x01ea<<2))
	#define P_nacten	            (U32*)(MPEG4BASE + (0x01eb<<2))
	#define P_Imcucnt_low	        (U32*)(MPEG4BASE + (0x01ec<<2))
	#define P_Imcucnt_high	        (U32*)(MPEG4BASE + (0x01ed<<2))
	#define P_Pmcucnt_low	        (U32*)(MPEG4BASE + (0x01ee<<2))
	#define P_Pmcucnt_high	        (U32*)(MPEG4BASE + (0x01ef<<2))
	#define P_Skipmcucnt_low        (U32*)(MPEG4BASE + (0x01f0<<2))
	#define P_Skipmcucnt_high       (U32*)(MPEG4BASE + (0x01f1<<2))
	#define P_H263_ctrl	            (U32*)(MPEG4BASE + (0x01f2<<2))
	#define P_setting_reg01f3       (U32*)(MPEG4BASE + (0x01f3<<2))
	#define P_HmvSum_low	        (U32*)(MPEG4BASE + (0x01f4<<2))
	#define P_HmvSum_high	        (U32*)(MPEG4BASE + (0x01f5<<2))
	#define P_VmvSum_low	        (U32*)(MPEG4BASE + (0x01f6<<2))
	#define P_VmvSum_high	        (U32*)(MPEG4BASE + (0x01f7<<2))
	#define P_TSram_ctrl	        (U32*)(MPEG4BASE + (0x01f8<<2))
	#define P_setting_reg01f9       (U32*)(MPEG4BASE + (0x01f9<<2))
	#define P_setting_reg01fa       (U32*)(MPEG4BASE + (0x01fa<<2))
	#define P_ROIMBXOffsetLSB       (U32*)(MPEG4BASE + (0x01fb<<2))
	#define P_ROIMBXDestLSB	        (U32*)(MPEG4BASE + (0x01fc<<2))
	#define P_ROIMBYOffsetLSB       (U32*)(MPEG4BASE + (0x01fd<<2))
	#define P_ROIMBYDestLSB	        (U32*)(MPEG4BASE + (0x01fe<<2))
	#define P_ROIMBMSB	            (U32*)(MPEG4BASE + (0x01ff<<2))
	// reg0200 ~ reg023f for HuffmanTable
	#define P_HuffmanTable_str	    (U32*)(MPEG4BASE + (0x0200<<2))
	#define P_HuffmanTable_end	    (U32*)(MPEG4BASE + (0x023f<<2))
	// reg0200 ~ reg023f for HuffmanTable
	//////////////////////////////////////////////////////////////////////////////
	#define P_HUFF_YDCW_REG	    	(U32*)(MPEG4BASE + (0x0200<<2))
	#define P_HUFF_YDCS_REG	    	(U32*)(MPEG4BASE + (0x0218<<2))
	#define P_HUFF_YDCV_REG	    	(U32*)(MPEG4BASE + (0x0220<<2))
	
	#define P_HUFF_CDCW_REG	    	(U32*)(MPEG4BASE + (0x0230<<2))
	#define P_HUFF_CDCS_REG	    	(U32*)(MPEG4BASE + (0x0248<<2))
	#define P_HUFF_CDCV_REG	    	(U32*)(MPEG4BASE + (0x0250<<2))
	
	#define P_HUFF_YACW_REG	    	(U32*)(MPEG4BASE + (0x0260<<2))
	#define P_HUFF_YACS_REG	    	(U32*)(MPEG4BASE + (0x0278<<2))
	
	#define P_HUFF_CACW_REG	    	(U32*)(MPEG4BASE + (0x0290<<2))
	#define P_HUFF_CACS_REG	    	(U32*)(MPEG4BASE + (0x02a8<<2))

/**
 * MIU2: 0x0823_0000 ~ 0x0823_FFFF
 */
#define MIU2BASE				0x88230000
	#define P_MIU2_SDRAM_SETTING    (U32*)(MIU2BASE + 0x00000060)
	#define P_MIU2_TV_START_ADR1    (U32*)(MIU2BASE + 0x00000044)
	#define P_MIU2_TV_START_ADR2    (U32*)(MIU2BASE + 0x00000048)
	#define P_MIU2_TV_START_ADR3    (U32*)(MIU2BASE + 0x00000064)
	
/**
 * ECC: 0x0824_0000 ~ 0x0824_FFFF
 */
#define ECCBASE					0x88240000

#endif	//SCOREIDE_SPG290_H_11538_14771__INCLUDED_

#endif	//_SYS_REGISTER_H