sys_register.h

凌阳32位单片机开发的小游戏

	#define P_DMA_AHB_SA1B			(U32*)(DMABASE + 0x0000004C)
	#define P_DMA_AHB_SA2B			(U32*)(DMABASE + 0x00000050)
	#define P_DMA_AHB_SA3B			(U32*)(DMABASE + 0x00000054)
	#define P_DMA_AHB_SA4B			(U32*)(DMABASE + 0x00000058)
	#define P_DMA_AHB_EA1B			(U32*)(DMABASE + 0x0000005C)
	#define P_DMA_AHB_EA2B			(U32*)(DMABASE + 0x00000060)
	#define P_DMA_AHB_EA3B			(U32*)(DMABASE + 0x00000064)
	#define P_DMA_AHB_EA4B			(U32*)(DMABASE + 0x00000068)
	#define P_DMA_CR1				(U32*)(DMABASE + 0x0000006C)
	#define P_DMA_CR2				(U32*)(DMABASE + 0x00000070)
	#define P_DMA_CR3				(U32*)(DMABASE + 0x00000074)
	#define P_DMA_CR4				(U32*)(DMABASE + 0x00000078)

/**
 * BUFCTL: 0x0809_0000 ~ 0x0809_FFFF
 */
#define BUFBASE					0x88090000
	#define P_C2P_SETTING           (U32*)(BUFBASE + 0x00000000)
	#define P_PTR_SETTING           (U32*)(BUFBASE + 0x00000004)
	#define P_CSI_BUF_PTR_REG       (U32*)(BUFBASE + 0x00000008)
	#define P_PPUT1_BUF_PTR_REG     (U32*)(BUFBASE + 0x0000000C)
	#define P_PPUT2_BUF_PTR_REG     (U32*)(BUFBASE + 0x00000010)
	#define P_PPUT3_BUF_PTR_REG     (U32*)(BUFBASE + 0x00000014)
	#define P_PPU_BUF_PTR_REG       (U32*)(BUFBASE + 0x00000018)
	#define P_JPG_BUF_PTR_REG       (U32*)(BUFBASE + 0x0000001C)
	#define P_TVE_BUF_PTR_REG       (U32*)(BUFBASE + 0x00000020)
	#define P_LCD_BUF_PTR_REG       (U32*)(BUFBASE + 0x00000024)
	#define P_BUFCTL_STATUS			(U32*)(BUFBASE + 0x00000028)				
	#define P_PPU_FRAME_CNT			(U32*)(BUFBASE + 0x0000002C)				
	#define P_PPU_FCNT_INC			(U32*)(BUFBASE + 0x00000030)				
	#define P_TVE_FRAME_CNT			(U32*)(BUFBASE + 0x00000034)				
	#define P_GPU_FRAME_END			(U32*)(BUFBASE + 0x00000038)				
	#define P_P2T_SETTING         	(U32*)(BUFBASE + 0x0000003C)
	#define P_P2L_SETTING			(U32*)(BUFBASE + 0x00000040)				
	#define P_MP4RAW_BUF_PTR_REG	(U32*)(BUFBASE + 0x00000044)				
	#define P_MP4W_BUF_PTR_REG		(U32*)(BUFBASE + 0x00000048)				
	#define P_BUFCTL_SETTING		(U32*)(BUFBASE + 0x0000004C)				
	#define P_MP4R_BUF_PTR_REG		(U32*)(BUFBASE + 0x00000050)		
	#define P_MP4V_BUF_PTR_REG		(U32*)(BUFBASE + 0x00000054)			
	#define P_HW4_SETTING			(U32*)(BUFBASE + 0x00000058)

/**
 * IRQCTL: 0x080A_0000 ~ 0x080A_FFFF
 */
#define IRQBASE					0x880A0000

/**
 * GPUBUF: 0x080B_0000 ~ 0x080B_FFFF
 */
#define GPUBASE					0x880B0000

/**
 * LDMDMA: 0x080C_0000 ~ 0x080C_FFFF
 */
#define LDMBASE					0x880c0000
	#define P_LDM_CTRL              (U32*)(LDMBASE + 0x00000000)
	#define P_LDM_STATUS            (U32*)(LDMBASE + 0x00000004)
	#define P_LDM_MIU_START         (U32*)(LDMBASE + 0x00000008)
	#define P_LDM_MIU_END           (U32*)(LDMBASE + 0x0000000C)
	#define P_LDM_START             (U32*)(LDMBASE + 0x00000010)
	#define P_LDM_END               (U32*)(LDMBASE + 0x00000014)

/**
 * BLNDMA: 0x080D_0000 ~ 0x080D_FFFF
 */
#define BLNDMABASE				0x880D0000
    #define P_BLNDMA_SRCA_ADDR		(U32*)(BLNDMABASE + 0x00000000)
	#define P_BLNDMA_SRCB_ADDR		(U32*)(BLNDMABASE + 0x00000004)
	#define P_BLNDMA_DEST_ADDR		(U32*)(BLNDMABASE + 0x00000008)
	#define P_BLNDMA_WIDTH_HEIGH	(U32*)(BLNDMABASE + 0x0000000C)
	#define P_BLNDMA_FILL_PAT		(U32*)(BLNDMABASE + 0x00000010)
	#define P_BLNDMA_CONTROL_1		(U32*)(BLNDMABASE + 0x00000014)
	#define P_BLNDMA_IRQ_CONTROL	(U32*)(BLNDMABASE + 0x00000018)
	#define P_BLNDMA_BLEND_FACTOR	(U32*)(BLNDMABASE + 0x0000001C)
	#define P_BLNDMA_TRANSPARENT	(U32*)(BLNDMABASE + 0x00000020)
	#define P_BLNDMA_ADDR_MODE		(U32*)(BLNDMABASE + 0x00000024)
	#define P_BLNDMA_CONTROL_2		(U32*)(BLNDMABASE + 0x00000028)
	#define P_BLNDMA_ABASE_ADDR		(U32*)(BLNDMABASE + 0x00000030)
	#define P_BLNDMA_AOFFSET_XY		(U32*)(BLNDMABASE + 0x00000034)
	#define P_BLNDMA_A_BG			(U32*)(BLNDMABASE + 0x00000038)
	#define P_BLNDMA_BBASE_ADDR		(U32*)(BLNDMABASE + 0x00000040)
	#define P_BLNDMA_BOFFSET_XY		(U32*)(BLNDMABASE + 0x00000044)
	#define P_BLNDMA_B_BG			(U32*)(BLNDMABASE + 0x00000048)
	#define P_BLNDMA_DBASE_ADDR		(U32*)(BLNDMABASE + 0x00000050)
	#define P_BLNDMA_DOFFSET_XY		(U32*)(BLNDMABASE + 0x00000054)
	#define P_BLNDMA_D_BG			(U32*)(BLNDMABASE + 0x00000058)

/**
 * TPGBUF: 0x080E_0000 ~ 0x080E_FFFF
 */
#define TPGBASE					0x880E0000

/**
 * AHBDEC: 0x080F_0000 ~ 0x080F_FFFF
 */
#define AHBDECBASE				0x880F0000

/**
 * GPIO: 0x0810_0000 ~ 0x0810_FFFF
 */
#define GPIOBASE				0x88100000
	#define	P_GPIO_TDR				(U32*)(GPIOBASE + 0x00000000)

/**
 * SPI: 0x0811_0000 ~ 0x0811_FFFF
 */
#define SPIBASE					0x88110000
	#define P_SPI_CTRL				(U32*)(SPIBASE + 0x00000000)
	#define P_SPI_TXSTS				(U32*)(SPIBASE + 0x00000004)
	#define P_SPI_TXDATA			(U32*)(SPIBASE + 0x00000008)
	#define P_SPI_RXSTS				(U32*)(SPIBASE + 0x0000000c)
	#define P_SPI_RXDATA			(U32*)(SPIBASE + 0x00000010)
	#define P_SPI_MISC				(U32*)(SPIBASE + 0x00000014)

/**
 * SIO: 0x0812_0000 ~ 0x0812_FFFF
 */
#define SIOBASE				0x88120000

/**
 * I2C: 0x0813_0000 ~ 0x0813_FFFF
 */
#define I2CBASE					0x88130000
	#define P_I2CCR					(U32*)(I2CBASE + 0x00000020)
	#define P_I2CINTR				(U32*)(I2CBASE + 0x00000024)
	#define P_I2CCVR				(U32*)(I2CBASE + 0x00000028)
	#define P_I2CID					(U32*)(I2CBASE + 0x0000002C)
	#define P_I2CADDR				(U32*)(I2CBASE + 0x00000030)
	#define P_I2CWDATA				(U32*)(I2CBASE + 0x00000034)
	#define P_I2CRDATA				(U32*)(I2CBASE + 0x00000038)
	#define	P_I2CPR					(U32*)(I2CBASE + 0x0000003C)

/**
 * I2S: 0x0814_0000 ~ 0x0814_FFFF
 */
#define I2SBASE					0x88140000
	#define P_I2S_CTRL				(U32*)(I2SBASE + 0x00000000)
	#define P_I2S_STAT				(U32*)(I2SBASE + 0x00000004)
	#define P_I2S_FIFO				(U32*)(I2SBASE + 0x00000008)
	#define P_I2S_DATA				(U32*)(I2SBASE + 0x0000000c)

/**
 * UART: 0x0815_0000 ~ 0x0815_FFFF
 */
#define UARTBASE				0x88150000
	#define P_UARTDR				(U32*)(UARTBASE+(0x00<<2))
	#define P_UARTRSR				(U32*)(UARTBASE+(0x01<<2))
	#define P_UARTCR				(U32*)(UARTBASE+(0x02<<2))
	#define P_UARTBUD				(U32*)(UARTBASE+(0x03<<2))
	#define P_UARTFR				(U32*)(UARTBASE+(0x04<<2))
	#define P_IRDACR				(U32*)(UARTBASE+(0x08<<2))
	#define P_UARTBMR				(U32*)(UARTBASE+(0x07<<2))
	#define P_TUBEDR				(U32*)(UARTBASE + 0x7ffc)

/**
 * TIMER1: 0x0816_0000 ~ 0x0816_0FFF
 */
#define TM0BASE					0x88160000
	#define P_TM0_CTRL				(U32*)(TM0BASE + 0x00000000)
	#define P_TM0_CCP_CTRL			(U32*)(TM0BASE + 0x00000004)
	#define P_TM0_PRELOAD			(U32*)(TM0BASE + 0x00000008)
	#define P_TM0_CCP_REG			(U32*)(TM0BASE + 0x0000000c)
	#define P_TM0_UPCNT				(U32*)(TM0BASE + 0x00000010)

/**
 * TIMER2: 0x0816_1000 ~ 0x0816_1FFF
 */
#define TM1BASE					0x88161000
	#define P_TM1_CTRL				(U32*)(TM1BASE + 0x00000000)
	#define P_TM1_CCP_CTRL			(U32*)(TM1BASE + 0x00000004)
	#define P_TM1_PRELOAD			(U32*)(TM1BASE + 0x00000008)
	#define P_TM1_CCP_REG			(U32*)(TM1BASE + 0x0000000c)
	#define P_TM1_UPCNT				(U32*)(TM1BASE + 0x00000010)

/**
 * TIMER3: 0x0816_2000 ~ 0x0816_2FFF
 */
#define TM2BASE					0x88162000
	#define P_TM2_CTRL				(U32*)(TM2BASE + 0x00000000)
	#define P_TM2_CCP_CTRL			(U32*)(TM2BASE + 0x00000004)
	#define P_TM2_PRELOAD			(U32*)(TM2BASE + 0x00000008)
	#define P_TM2_CCP_REG			(U32*)(TM2BASE + 0x0000000c)
	#define P_TM2_UPCNT				(U32*)(TM2BASE + 0x00000010)

/**
 * TIMER4: 0x0816_3000 ~ 0x0816_3FFF
 */
#define TM3BASE					0x88163000
	#define P_TM3_CTRL				(U32*)(TM3BASE + 0x00000000)
	#define P_TM3_CCP_CTRL			(U32*)(TM3BASE + 0x00000004)
	#define P_TM3_PRELOAD			(U32*)(TM3BASE + 0x00000008)
	#define P_TM3_CCP_REG			(U32*)(TM3BASE + 0x0000000c)
	#define P_TM3_UPCNT				(U32*)(TM3BASE + 0x00000010)

/**
 * TIMER5: 0x0816_4000 ~ 0x0816_4FFF
 */
#define TM4BASE					0x88164000
	#define P_TM4_CTRL				(U32*)(TM4BASE + 0x00000000)
	#define P_TM4_CCP_CTRL			(U32*)(TM4BASE + 0x00000004)
	#define P_TM4_PRELOAD			(U32*)(TM4BASE + 0x00000008)
	#define P_TM4_CCP_REG			(U32*)(TM4BASE + 0x0000000c)
	#define P_TM4_UPCNT				(U32*)(TM4BASE + 0x00000010)

/**
 * TIMER6: 0x0816_5000 ~ 0x0816_5FFF
 */
#define TM5BASE					0x88165000
	#define P_TM5_CTRL				(U32*)(TM5BASE + 0x00000000)
	#define P_TM5_CCP_CTRL			(U32*)(TM5BASE + 0x00000004)
	#define P_TM5_PRELOAD			(U32*)(TM5BASE + 0x00000008)
	#define P_TM5_CCP_REG			(U32*)(TM5BASE + 0x0000000c)
	#define P_TM5_UPCNT				(U32*)(TM5BASE + 0x00000010)

/**
 * RTC: 0x0816_6000 ~ 0x0816_6FFF
 */
#define RTCBASE					0x88166000
	#define P_RTC_RTCSEC			(U32*)(RTCBASE + 0x00000000)
	#define P_RTC_RTCMIN			(U32*)(RTCBASE + 0x00000004)
	#define P_RTC_RTCHOU			(U32*)(RTCBASE + 0x00000008)
	#define P_RTC_ALMSEC			(U32*)(RTCBASE + 0x0000000c)
	#define P_RTC_ALMMIN			(U32*)(RTCBASE + 0x00000010)
	#define P_RTC_ALMHOU			(U32*)(RTCBASE + 0x00000014)
	#define P_RTC_CTRL1				(U32*)(RTCBASE + 0x00000018)
	#define P_RTC_STST1				(U32*)(RTCBASE + 0x0000001c)
	#define P_RTC_CTRL2				(U32*)(RTCBASE + 0x00000020)
	#define P_RTC_STST2				(U32*)(RTCBASE + 0x00000024)
	#define P_RTC_RESET				(U32*)(RTCBASE + 0x00000028)

/**
 * WDOG: 0x0817_0000 ~ 0x0817_FFFF
 */
#define WDGBASE					0x88170000
	#define P_WDG_CTRL				(U32*)(WDGBASE + 0x00000000)
	#define P_WDG_CYC				(U32*)(WDGBASE + 0x00000004)
	#define P_WDG_CLR				(U32*)(WDGBASE + 0x00000008)

/**
 * SD: 0x0818_0000 ~ 0x0818_FFFF
 */
#define SDCBASE					0x88180000
	#define P_SDC_DataTx           	(U32*)(SDCBASE + 0x00000000)
	#define P_SDC_DataRx           	(U32*)(SDCBASE + 0x00000004)
	#define P_SDC_Command          	(U32*)(SDCBASE + 0x00000008)
	#define P_SDC_Arg              	(U32*)(SDCBASE + 0x0000000C)
	#define P_SDC_Resp             	(U32*)(SDCBASE + 0x00000010)
	#define P_SDC_Status           	(U32*)(SDCBASE + 0x00000014)
	#define P_SDC_Control          	(U32*)(SDCBASE + 0x00000018)
	#define P_SDC_IntEn            	(U32*)(SDCBASE + 0x0000001C)

/**
 * FLASH: 0x0819_0000 ~ 0x0819_FFFF
 */
#define FLCBASE					0x88190000
	#define P_FL_CR					(U32*)(FLCBASE + 0x00000000)
	#define P_FL_CLE				(U32*)(FLCBASE + 0x00000004)
	#define P_FL_ALE				(U32*)(FLCBASE + 0x00000008)
	#define P_FL_WD					(U32*)(FLCBASE + 0x0000000C)
	#define P_FL_RD					(U32*)(FLCBASE + 0x00000010)
	#define P_FL_INTEN				(U32*)(FLCBASE + 0x00000014)
	#define P_FL_INTSTS				(U32*)(FLCBASE + 0x00000018)
	#define P_FL_TRUELP				(U32*)(FLCBASE + 0x0000001C)
	#define P_FL_TRUECP				(U32*)(FLCBASE + 0x00000020)
	#define P_FL_CALLP				(U32*)(FLCBASE + 0x00000024)
	#define P_FL_CALCP				(U32*)(FLCBASE + 0x00000028)
	#define P_FL_ECCSTS				(U32*)(FLCBASE + 0x0000002C)
	#define P_FL_CALECC				(U32*)(FLCBASE + 0x00000030)

/**
 * ADC: 0x081A_0000 ~ 0x081A_FFFF
 */
#define ADCBASE					0x881a0000
	#define P_ADC_SETUP				(U32*)(ADCBASE + 0x00000000)