📄 sys_register.h
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/******************************************************************************
*
* The information contained herein is the exclusive property of
* Sunplus Technology Co. And shall not be distributed, reproduced,
* or disclosed in whole in part without prior written permission.
*
* (C) COPYRIGHT 2005 SUNPLUS TECHNOLOGY CO.
* ALL RIGHTS RESERVED
*
* The entire notice above must be reproduced on all authorized copies.
*
*****************************************************************************/
/******************************************************************************
* Filename: Sys_Register.h
* Author: Robin.xjliu (eMail: xjliu@sunplus.com)
* Tel: 00885-028-87848688-5884
* Date: 2005-11-03
* Description: all the SPG290 Register define
* Reference:
* Version history:
*-----------------------------------------------------------------------------
* Version YYYY-MM-DD-INDEX Modified By Description
* 1.0.0 2005-11-03 xjliu Create
*
*****************************************************************************/
#ifndef _SYS_REGISTER_H
#define _SYS_REGISTER_H
#include "Sys_Define.h"
#ifndef SCOREIDE_SPG290_H_11538_14771__INCLUDED_
#define SCOREIDE_SPG290_H_11538_14771__INCLUDED_
/**
* general register define
*/
typedef union
{
U32 DW;
struct
{
U32 bit0 : 1;
U32 bit1 : 1;
U32 bit2 : 1;
U32 bit3 : 1;
U32 bit4 : 1;
U32 bit5 : 1;
U32 bit6 : 1;
U32 bit7 : 1;
U32 bit8 : 1;
U32 bit9 : 1;
U32 bit10 : 1;
U32 bit11 : 1;
U32 bit12 : 1;
U32 bit13 : 1;
U32 bit14 : 1;
U32 bit15 : 1;
U32 ReservedH :16;
} B;
}GEN_REG_DEF;
/**
* P_SP_Control(0x88010004) register define
*/
typedef union
{
U32 DW;
struct
{
U32 Sp_en : 1;
U32 Coord_sel : 1;
U32 Reserved :14;
U32 ReservedH :16;
} B;
}P_Sp_Control_DEF;
/**
* CSI: 0x0800_0000 ~ 0x0800_FFFF
*/
#define CSIBASE 0x88000000
#define P_CSI_TG_CR (U32*)(CSIBASE + 0x00000000)
#define P_CSI_TG_LSTART (U32*)(CSIBASE + 0x00000004)
#define P_CSI_TG_START (U32*)(CSIBASE + 0x00000008)
#define P_CSI_TG_END (U32*)(CSIBASE + 0x0000000C)
#define P_CSI_TG_BLACK (U32*)(CSIBASE + 0x00000010)
#define P_CSI_TG_BSUPPER (U32*)(CSIBASE + 0x00000014)
#define P_CSI_TG_BSLOWER (U32*)(CSIBASE + 0x00000018)
#define P_CSI_TG_TRANSP (U32*)(CSIBASE + 0x0000001C)
#define P_CSI_TG_FBSADDR0 (U32*)(CSIBASE + 0x00000020)
#define P_CSI_TG_FBSADDR1 (U32*)(CSIBASE + 0x00000024)
#define P_CSI_TG_FBSADDR2 (U32*)(CSIBASE + 0x00000028)
#define P_CSI_TG_CAP (U32*)(CSIBASE + 0x0000002C)
#define P_CSI_MD_CR (U32*)(CSIBASE + 0x00000030)
#define P_CSI_MD_SADDR (U32*)(CSIBASE + 0x00000034)
#define P_CSI_MD_POS (U32*)(CSIBASE + 0x00000038)
#define P_CSI_MD_SADDR1 (U32*)(CSIBASE + 0x0000003C)
#define P_CSI_MD_CTABLE0 (U32*)(CSIBASE + 0x00000040)
#define P_CSI_MD_CTABLE1 (U32*)(CSIBASE + 0x00000044)
#define P_CSI_MD_CTABLE2 (U32*)(CSIBASE + 0x00000048)
#define P_CSI_MD_CTABLE3 (U32*)(CSIBASE + 0x0000004C)
#define P_CSI_MD_REG1 (U32*)(CSIBASE + 0x00000050)
#define P_CSI_MD_REG2 (U32*)(CSIBASE + 0x00000054)
#define P_CSI_MD_REG3 (U32*)(CSIBASE + 0x00000058)
#define P_CSI_MD_TH (U32*)(CSIBASE + 0x0000005C)
#define P_CSI_MD_YUV (U32*)(CSIBASE + 0x00000070)
#define P_CSI_MD_RGB (U32*)(CSIBASE + 0x00000074)
#define P_CSI_IRQEN (U32*)(CSIBASE + 0x00000078)
#define P_CSI_IRQSTS (U32*)(CSIBASE + 0x0000007C)
#define P_CSI_Y2R_A1 (U32*)(CSIBASE + 0x000000E8)
#define P_CSI_Y2R_A2 (U32*)(CSIBASE + 0x000000EC)
#define P_CSI_Y2R_A3 (U32*)(CSIBASE + 0x000000F0)
#define P_CSI_R2Y_A1 (U32*)(CSIBASE + 0x000000F4)
#define P_CSI_R2Y_A2 (U32*)(CSIBASE + 0x000000F8)
#define P_CSI_R2Y_A3 (U32*)(CSIBASE + 0x000000FC)
/**
* PPU: 0x0801_0000 ~ 0x0801_FFFF
*/
#define PPUBASE 0x88010000
#define P_PPU_CONTROL (U32*)(PPUBASE + 0x00000000)
#define P_SP_Control ((volatile P_Sp_Control_DEF *) (PPUBASE + 0x00000004))
#define P_SP_MAX (U32*)(PPUBASE + 0x00000008)
#define P_BLN_FORMULA (U32*)(PPUBASE + 0x0000000C)
#define P_TRANS_RGB (U32*)(PPUBASE + 0x00000010)
#define P_PPU_TX1_X (U32*)(PPUBASE + 0x00000020)
#define P_PPU_TX1_Y (U32*)(PPUBASE + 0x00000024)
#define P_PPU_TX1_Attribute (U32*)(PPUBASE + 0x00000028)
#define P_PPU_TX1_Control (U32*)(PPUBASE + 0x0000002C)
#define P_PPU_TX1_N_PTR (U32*)(PPUBASE + 0x00000030)
#define P_PPU_TX1_Blending (U32*)(PPUBASE + 0x00000038)
#define P_PPU_TX2_X (U32*)(PPUBASE + 0x0000003C)
#define P_PPU_TX2_Y (U32*)(PPUBASE + 0x00000040)
#define P_PPU_TX2_Attribute (U32*)(PPUBASE + 0x00000044)
#define P_PPU_TX2_Control (U32*)(PPUBASE + 0x00000048)
#define P_PPU_TX2_N_PTR (U32*)(PPUBASE + 0x0000004C)
#define P_PPU_TX2_Blending (U32*)(PPUBASE + 0x00000054)
#define P_PPU_TX3_X (U32*)(PPUBASE + 0x00000058)
#define P_PPU_TX3_Y (U32*)(PPUBASE + 0x0000005C)
#define P_PPU_TX3_Attribute (U32*)(PPUBASE + 0x00000060)
#define P_PPU_TX3_Control (U32*)(PPUBASE + 0x00000064)
#define P_PPU_TX3_N_PTR (U32*)(PPUBASE + 0x00000068)
#define P_PPU_TX3_Blending (U32*)(PPUBASE + 0x00000070)
#define P_PPU_VComp_Value (U32*)(PPUBASE + 0x00000074)
#define P_PPU_VComp_Offset (U32*)(PPUBASE + 0x00000078)
#define P_PPU_VComp_Step (U32*)(PPUBASE + 0x0000007C)
#define P_IRQ_CONTROL (U32*)(PPUBASE + 0x00000080)
#define P_IRQ_STATUS (U32*)(PPUBASE + 0x00000084)
#define P_IRQ_TMV (U32*)(PPUBASE + 0x00000088)
#define P_IRQ_TMH (U32*)(PPUBASE + 0x0000008C)
#define P_VBLK_TIME (U32*)(PPUBASE + 0x00000090)
#define P_LINE_COUNTER (U32*)(PPUBASE + 0x00000094)
#define P_PPU_TX1_START_ADR1 (U32*)(PPUBASE + 0x000000A0)
#define P_PPU_TX1_START_ADR2 (U32*)(PPUBASE + 0x000000A4)
#define P_PPU_TX1_START_ADR3 (U32*)(PPUBASE + 0x000000A8)
#define P_PPU_TX2_START_ADR1 (U32*)(PPUBASE + 0x000000AC)
#define P_PPU_TX2_START_ADR2 (U32*)(PPUBASE + 0x000000B0)
#define P_PPU_TX2_START_ADR3 (U32*)(PPUBASE + 0x000000B4)
#define P_PPU_TX3_START_ADR1 (U32*)(PPUBASE + 0x000000B8)
#define P_PPU_TX3_START_ADR2 (U32*)(PPUBASE + 0x000000BC)
#define P_PPU_TX3_START_ADR3 (U32*)(PPUBASE + 0x000000C0)
#define P_PPU_FB_START_ADR1 (U32*)(PPUBASE + 0x000000C4)
#define P_PPU_FB_START_ADR2 (U32*)(PPUBASE + 0x000000C8)
#define P_PPU_FB_START_ADR3 (U32*)(PPUBASE + 0x000000CC)
#define P_SP_BUF_SA ((volatile GEN_REG_DEF *) (PPUBASE + 0x000000D0))
#define P_BG_COLOR_PALETTE (U32*)(PPUBASE + 0x00001000)
#define P_SP_COLOR_PALETTE (U32*)(PPUBASE + 0x00001800)
#define P_PPU_Tx_HOffset_ADR (U32*)(PPUBASE + 0x00002000)
#define P_PPU_Tx1_HCmp_ADR (U32*)(PPUBASE + 0x00003000)
#define P_PPU_Sprite (U32*)(PPUBASE + 0x00004000)
/**
* JPG: 0x0802_0000 ~ 0x0802_FFFF
*/
#define JPGBASE 0x88020000
/**
* TV: 0x0803_0000 ~ 0x0803_FFFF
*/
#define TVEBASE 0x88030000
#define P_TV_CONTROL (U32*)(TVEBASE + 0x00000000)
#define P_TV_SAT (U32*)(TVEBASE + 0x00000004)
#define P_TV_HUE (U32*)(TVEBASE + 0x00000008)
#define P_TV_FADE (U32*)(TVEBASE + 0x0000000C)
#define P_TV_ACT_START (U32*)(TVEBASE + 0x00000010)
#define P_TV_ACT_END (U32*)(TVEBASE + 0x00000014)
#define P_TV_IRQTMV (U32*)(TVEBASE + 0x00000018)
#define P_TV_IRQTMH (U32*)(TVEBASE + 0x0000001C)
#define P_TV_LINECON (U32*)(TVEBASE + 0x00000020)
#define P_TV_TEST (U32*)(TVEBASE + 0x0000003C)
#define P_TV_LPCON (U32*)(TVEBASE + 0x00000040)
#define P_TV_LPV (U32*)(TVEBASE + 0x00000044)
#define P_TV_LPH (U32*)(TVEBASE + 0x00000048)
/**
* LCD: 0x0804_0000 ~ 0x0804_FFFF
*/
#define LCDBASE 0x88040000
/**
* SPU: 0x0805_0000 ~ 0x0805_FFFF
*/
#define SPUBASE 0x88050000
/**
* CD: 0x0806_0000 ~ 0x0806_FFFF
*/
#define CDBASE 0x88060000
/**
* MIU1: 0x0807_0000 ~ 0x0807_FFFF
*/
#define MIU1BASE 0x88070000
#define P_CSI_START_ADR1 (U32*)(MIU1BASE + 0x00000000)
#define P_CSI_START_ADR2 (U32*)(MIU1BASE + 0x00000004)
#define P_CSI_START_ADR3 (U32*)(MIU1BASE + 0x00000008)
#define P_PPU_TEXT1_START_ADR1 (U32*)(MIU1BASE + 0x0000000C)
#define P_PPU_TEXT1_START_ADR2 (U32*)(MIU1BASE + 0x00000010)
#define P_PPU_TEXT1_START_ADR3 (U32*)(MIU1BASE + 0x00000014)
#define P_PPU_TEXT2_START_ADR1 (U32*)(MIU1BASE + 0x00000018)
#define P_PPU_TEXT2_START_ADR2 (U32*)(MIU1BASE + 0x0000001C)
#define P_PPU_TEXT2_START_ADR3 (U32*)(MIU1BASE + 0x00000020)
#define P_PPU_TEXT3_START_ADR1 (U32*)(MIU1BASE + 0x00000024)
#define P_PPU_TEXT3_START_ADR2 (U32*)(MIU1BASE + 0x00000028)
#define P_PPU_TEXT3_START_ADR3 (U32*)(MIU1BASE + 0x0000002C)
#define P_PPU_START_ADR1 (U32*)(MIU1BASE + 0x00000030)
#define P_PPU_START_ADR2 (U32*)(MIU1BASE + 0x00000034)
#define P_JPG_START_ADR1 (U32*)(MIU1BASE + 0x00000038)
#define P_JPG_START_ADR2 (U32*)(MIU1BASE + 0x0000003C)
#define P_JPGB_START_ADR (U32*)(MIU1BASE + 0x00000040)
#define P_TV_START_ADR1 (U32*)(MIU1BASE + 0x00000044)
#define P_TV_START_ADR2 (U32*)(MIU1BASE + 0x00000048)
#define P_LCD_START_ADR1 (U32*)(MIU1BASE + 0x0000004C)
#define P_LCD_START_ADR2 (U32*)(MIU1BASE + 0x00000050)
#define P_SPU_START_ADR (U32*)(MIU1BASE + 0x00000054)
#define P_CD_START_ADR (U32*)(MIU1BASE + 0x00000058)
#define P_SDRAM_POWER_DOWN (U32*)(MIU1BASE + 0x0000005C)
#define P_MIU1_SDRAM_SETTING (U32*)(MIU1BASE + 0x00000060)
#define P_TV_START_ADR3 (U32*)(MIU1BASE + 0x00000064)
#define P_LCD_START_ADR3 (U32*)(MIU1BASE + 0x00000068)
#define P_SET_FLASH_CTL (U32*)(MIU1BASE + 0x00000100)
#define P_SET_BT_BTC (U32*)(MIU1BASE + 0x00000104)
#define P_MP4RAW_START_ADR1 (U32*)(MIU1BASE + 0x00000070)
#define P_MP4RAW_START_ADR2 (U32*)(MIU1BASE + 0x00000074)
#define P_MP4RAW_START_ADR3 (U32*)(MIU1BASE + 0x00000078)
#define P_MP4W_START_ADR1 (U32*)(MIU1BASE + 0x0000007c)
#define P_MP4W_START_ADR2 (U32*)(MIU1BASE + 0x00000080)
#define P_MP4W_START_ADR3 (U32*)(MIU1BASE + 0x00000084)
#define P_MP4V_START_ADR1 (U32*)(MIU1BASE + 0x00000088)
#define P_MP4V_START_ADR2 (U32*)(MIU1BASE + 0x0000008c)
#define P_MP4_FRAME_BUF_HSIZE (U32*)(MIU1BASE + 0x00000090)
/**
* APBDMA: 0x0808_0000 ~ 0x0808_FFFF
*/
#define DMABASE 0x88080000
#define P_DMA_BSY (U32*)(DMABASE + 0x00000000)
#define P_DMA_INT (U32*)(DMABASE + 0x00000004)
#define P_DMA_AHB_SA1A (U32*)(DMABASE + 0x00000008)
#define P_DMA_AHB_SA2A (U32*)(DMABASE + 0x0000000c)
#define P_DMA_AHB_SA3A (U32*)(DMABASE + 0x00000010)
#define P_DMA_AHB_SA4A (U32*)(DMABASE + 0x00000014)
#define P_DMA_AHB_EA1A (U32*)(DMABASE + 0x00000018)
#define P_DMA_AHB_EA2A (U32*)(DMABASE + 0x0000001c)
#define P_DMA_AHB_EA3A (U32*)(DMABASE + 0x00000020)
#define P_DMA_AHB_EA4A (U32*)(DMABASE + 0x00000024)
#define P_DMA_APB_SA1 (U32*)(DMABASE + 0x00000028)
#define P_DMA_APB_SA2 (U32*)(DMABASE + 0x0000002c)
#define P_DMA_APB_SA3 (U32*)(DMABASE + 0x00000030)
#define P_DMA_APB_SA4 (U32*)(DMABASE + 0x00000034)
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