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PTD_SWR mx1hw.h 763;" dPWM1_BASE_ADDR mx1hw.h 922;" dPWMC1 mx1hw.h 923;" dPWMCNT1 mx1hw.h 926;" dPWMP1 mx1hw.h 925;" dPWMS1 mx1hw.h 924;" dPWMTST1 mx1hw.h 927;" dP_AREA khead.h /^} AREA, *P_AREA;$/;" tP_POINT khead.h /^} POINT, *P_POINT;$/;" tP_S16 khead.h /^typedef S16 *P_S16; \/* signed 16 bit data *\/$/;" tP_S32 khead.h /^typedef S32 *P_S32; \/* signed 32 bit data *\/$/;" tP_S8 khead.h /^typedef S8 *P_S8; \/* signed 8 bit data *\/$/;" tP_TEXT khead.h /^typedef P_U16 P_TEXT; \/* 16-bit text data *\/$/;" tP_U16 khead.h /^typedef U16 *P_U16; \/* unsigned 16 bit data *\/$/;" tP_U32 khead.h /^typedef U32 *P_U32; \/* unsigned 32 bit data *\/$/;" tP_U8 khead.h /^typedef U8 *P_U8; \/* unsigned 8 bit data *\/$/;" tP_VOID khead.h /^typedef void *P_VOID; \/* pointer to void *\/$/;" tRAM1_BASE_ADDR mx1hw.h 934;" dRAM1_END_ADDR mx1hw.h 935;" dRAM2_BASE_ADDR mx1hw.h 936;" dRAM2_END_ADDR mx1hw.h 937;" dRS_set_level im8803.c /^void RS_set_level(U32 level)$/;" fRTC_ALRM_HM mx1hw.h 947;" dRTC_ALRM_SEC mx1hw.h 948;" dRTC_BASE_ADDR mx1hw.h 944;" dRTC_DAYALARM mx1hw.h 954;" dRTC_DAYR mx1hw.h 953;" dRTC_HOURMIN mx1hw.h 945;" dRTC_RTCCTL mx1hw.h 949;" dRTC_RTCIENR mx1hw.h 951;" dRTC_RTCISR mx1hw.h 950;" dRTC_SECOND mx1hw.h 946;" dRTC_STPWCH mx1hw.h 952;" dRTC_TEST1 mx1hw.h 955;" dRTC_TEST2 mx1hw.h 956;" dRTC_TEST3 mx1hw.h 957;" dS16 khead.h /^typedef short S16; \/* signed 16 bit data *\/$/;" tS32 khead.h /^typedef long S32; \/* signed 32 bit data *\/$/;" tS8 khead.h /^typedef signed char S8; \/* signed 8 bit data *\/$/;" tSA_R i2c.h 12;" dSA_W i2c.h 11;" dSCM20014_ADDR_R csi2c.h 32;" dSCM20014_ADDR_W csi2c.h 31;" dSDRAM0_BASE mx1hw.h 1241;" dSDRAM0_END_ADDR mx1hw.h 1243;" dSDRAM1_BASE mx1hw.h 1242;" dSDRAM1_END_ADDR mx1hw.h 1244;" dSDRAMC_BASE_ADDR mx1hw.h 963;" dSDRAMC_SDCTL0 mx1hw.h 964;" dSDRAMC_SDCTL1 mx1hw.h 965;" dSFCM_capture_DMA dma.c /^static U32 SFCM_capture_DMA(U32 nPixel)$/;" f file:SIM_BASE_ADDR mx1hw.h 971;" dSIM_CHAR_WAIT mx1hw.h 986;" dSIM_CNTL mx1hw.h 973;" dSIM_DIVISOR mx1hw.h 988;" dSIM_ENABLE mx1hw.h 975;" dSIM_GPCNT mx1hw.h 987;" dSIM_GUARD_CNTL mx1hw.h 983;" dSIM_INT_MASK mx1hw.h 978;" dSIM_OD_CONFIG mx1hw.h 984;" dSIM_PORT_CNTL mx1hw.h 972;" dSIM_PORT_DETECT mx1hw.h 981;" dSIM_PORT_RCV_BUF mx1hw.h 980;" dSIM_PORT_XMT_BUF mx1hw.h 979;" dSIM_RCV_STATUS mx1hw.h 977;" dSIM_RCV_THRESHOLD mx1hw.h 974;" dSIM_RESET_CNTL mx1hw.h 985;" dSIM_XMT_STATUS mx1hw.h 976;" dSIM_XMT_THRESHOLD mx1hw.h 982;" dSINT16 khead.h /^typedef signed short SINT16;$/;" tSINT32 khead.h /^typedef signed long SINT32;$/;" tSINT8 khead.h /^typedef signed char SINT8;$/;" tSOFseqNum csi2c.c /^static U32 SOFseqNum;$/;" v file:SSI_BASE_ADDR mx1hw.h 821;" dSSI_SCSR mx1hw.h 824;" dSSI_SFCSR mx1hw.h 830;" dSSI_SOR mx1hw.h 832;" dSSI_SRCCR mx1hw.h 828;" dSSI_SRCR mx1hw.h 826;" dSSI_SRX mx1hw.h 823;" dSSI_STCCR mx1hw.h 827;" dSSI_STCR mx1hw.h 825;" dSSI_STR mx1hw.h 831;" dSSI_STSR mx1hw.h 829;" dSSI_STX mx1hw.h 822;" dSTATUS khead.h /^typedef U16 STATUS;$/;" tSTOP_PH mx1hw.h 890;" dSTOP_PORTHOLE mx1hw.h 889;" dSVC_STACK mx1hw.h 185;" dTBIT mx1hw.h 160;" dTEXT khead.h /^typedef U16 TEXT; \/* 16-bit text data *\/$/;" tTIMER1_BASE_ADDR mx1hw.h 994;" dTIMER1_TCMP1 mx1hw.h 997;" dTIMER1_TCN1 mx1hw.h 999;" dTIMER1_TCR1 mx1hw.h 998;" dTIMER1_TCTL1 mx1hw.h 995;" dTIMER1_TPRER1 mx1hw.h 996;" dTIMER1_TSTAT1 mx1hw.h 1000;" dTIMER2_BASE_ADDR mx1hw.h 1006;" dTIMER2_TCMP2 mx1hw.h 1009;" dTIMER2_TCN2 mx1hw.h 1011;" dTIMER2_TCR2 mx1hw.h 1010;" dTIMER2_TCTL2 mx1hw.h 1007;" dTIMER2_TPRER2 mx1hw.h 1008;" dTIMER2_TSTAT2 mx1hw.h 1012;" dTOP_OF_STACK mx1hw.h 938;" dTRUE khead.h 27;" dTUBEDataMask mx1hw.h 1021;" dTUBEDataOff mx1hw.h 1020;" dTestFrameSize test.c /^void TestFrameSize(void)$/;" fTubeBase mx1hw.h 1019;" dU16 khead.h /^typedef unsigned short U16; \/* unsigned 16 bit data *\/$/;" tU32 khead.h /^typedef unsigned int U32; \/* unsigned 32 bit data *\/$/;" tU8 khead.h /^typedef unsigned char U8; \/* unsigned 8 bit data *\/$/;" tUART1_BASE_ADDR mx1hw.h 1030;" dUART1_BIPR1 mx1hw.h 1045;" dUART1_BIPR2 mx1hw.h 1047;" dUART1_BIPR3 mx1hw.h 1049;" dUART1_BIPR4 mx1hw.h 1051;" dUART1_BIR mx1hw.h 1042;" dUART1_BMPR1 mx1hw.h 1046;" dUART1_BMPR2 mx1hw.h 1048;" dUART1_BMPR3 mx1hw.h 1050;" dUART1_BMPR4 mx1hw.h 1052;" dUART1_BMR mx1hw.h 1043;" dUART1_BRC mx1hw.h 1044;" dUART1_CR1 mx1hw.h 1033;" dUART1_CR2 mx1hw.h 1034;" dUART1_CR3 mx1hw.h 1035;" dUART1_CR4 mx1hw.h 1036;" dUART1_ESC mx1hw.h 1040;" dUART1_FCR mx1hw.h 1037;" dUART1_RXDATA mx1hw.h 1031;" dUART1_SR1 mx1hw.h 1038;" dUART1_SR2 mx1hw.h 1039;" dUART1_TIM mx1hw.h 1041;" dUART1_TS mx1hw.h 1053;" dUART1_TXDATA mx1hw.h 1032;" dUART2_BASE_ADDR mx1hw.h 1059;" dUART2_BIPR1 mx1hw.h 1074;" dUART2_BIPR2 mx1hw.h 1076;" dUART2_BIPR3 mx1hw.h 1078;" dUART2_BIPR4 mx1hw.h 1080;" dUART2_BIR mx1hw.h 1071;" dUART2_BMPR1 mx1hw.h 1075;" dUART2_BMPR2 mx1hw.h 1077;" dUART2_BMPR3 mx1hw.h 1079;" dUART2_BMPR4 mx1hw.h 1081;" dUART2_BMR mx1hw.h 1072;" dUART2_BRC mx1hw.h 1073;" dUART2_CR1 mx1hw.h 1062;" dUART2_CR2 mx1hw.h 1063;" dUART2_CR3 mx1hw.h 1064;" dUART2_CR4 mx1hw.h 1065;" dUART2_ESC mx1hw.h 1069;" dUART2_FCR mx1hw.h 1066;" dUART2_RXDATA mx1hw.h 1060;" dUART2_SR1 mx1hw.h 1067;" dUART2_SR2 mx1hw.h 1068;" dUART2_TIM mx1hw.h 1070;" dUART2_TS mx1hw.h 1082;" dUART2_TXDATA mx1hw.h 1061;" dUINT16 khead.h /^typedef unsigned short UINT16;$/;" tUINT32 khead.h /^typedef unsigned long UINT32;$/;" tUINT8 khead.h /^typedef unsigned char UINT8;$/;" tUND_STACK mx1hw.h 189;" dUSBD_BASE_ADDR mx1hw.h 1088;" dUSBD_CTRL mx1hw.h 1092;" dUSBD_DADR mx1hw.h 1093;" dUSBD_DDAT mx1hw.h 1094;" dUSBD_ENABLE mx1hw.h 1098;" dUSBD_EP0_FALRM mx1hw.h 1108;" dUSBD_EP0_FCTRL mx1hw.h 1105;" dUSBD_EP0_FDAT mx1hw.h 1103;" dUSBD_EP0_FRDP mx1hw.h 1109;" dUSBD_EP0_FSTAT mx1hw.h 1104;" dUSBD_EP0_FWDP mx1hw.h 1110;" dUSBD_EP0_INTR mx1hw.h 1101;" dUSBD_EP0_LFRP mx1hw.h 1106;" dUSBD_EP0_LFWP mx1hw.h 1107;" dUSBD_EP0_MASK mx1hw.h 1102;" dUSBD_EP0_STAT mx1hw.h 1100;" dUSBD_EP1_FALRM mx1hw.h 1120;" dUSBD_EP1_FCTRL mx1hw.h 1117;" dUSBD_EP1_FDAT mx1hw.h 1115;" dUSBD_EP1_FRDP mx1hw.h 1121;" dUSBD_EP1_FSTAT mx1hw.h 1116;" dUSBD_EP1_FWDP mx1hw.h 1122;" dUSBD_EP1_INTR mx1hw.h 1113;" dUSBD_EP1_LFRP mx1hw.h 1118;" dUSBD_EP1_LFWP mx1hw.h 1119;" dUSBD_EP1_MASK mx1hw.h 1114;" dUSBD_EP1_STAT mx1hw.h 1112;" dUSBD_EP2_FALRM mx1hw.h 1132;" dUSBD_EP2_FCTRL mx1hw.h 1129;" dUSBD_EP2_FDAT mx1hw.h 1127;" dUSBD_EP2_FRDP mx1hw.h 1133;" dUSBD_EP2_FSTAT mx1hw.h 1128;" dUSBD_EP2_FWDP mx1hw.h 1134;" dUSBD_EP2_INTR mx1hw.h 1125;" dUSBD_EP2_LFRP mx1hw.h 1130;" dUSBD_EP2_LFWP mx1hw.h 1131;" dUSBD_EP2_MASK mx1hw.h 1126;" dUSBD_EP2_STAT mx1hw.h 1124;" dUSBD_EP3_FALRM mx1hw.h 1144;" dUSBD_EP3_FCTRL mx1hw.h 1141;" dUSBD_EP3_FDAT mx1hw.h 1139;" dUSBD_EP3_FRDP mx1hw.h 1145;" dUSBD_EP3_FSTAT mx1hw.h 1140;" dUSBD_EP3_FWDP mx1hw.h 1146;" dUSBD_EP3_INTR mx1hw.h 1137;" dUSBD_EP3_LFRP mx1hw.h 1142;" dUSBD_EP3_LFWP mx1hw.h 1143;" dUSBD_EP3_MASK mx1hw.h 1138;" dUSBD_EP3_STAT mx1hw.h 1136;" dUSBD_EP4_FALRM mx1hw.h 1156;" dUSBD_EP4_FCTRL mx1hw.h 1153;" dUSBD_EP4_FDAT mx1hw.h 1151;" dUSBD_EP4_FRDP mx1hw.h 1157;" dUSBD_EP4_FSTAT mx1hw.h 1152;" dUSBD_EP4_FWDP mx1hw.h 1158;" dUSBD_EP4_INTR mx1hw.h 1149;" dUSBD_EP4_LFRP mx1hw.h 1154;" dUSBD_EP4_LFWP mx1hw.h 1155;" dUSBD_EP4_MASK mx1hw.h 1150;" dUSBD_EP4_STAT mx1hw.h 1148;" dUSBD_EP5_FALRM mx1hw.h 1167;" dUSBD_EP5_FCTRL mx1hw.h 1164;" dUSBD_EP5_FDAT mx1hw.h 1162;" dUSBD_EP5_FRDP mx1hw.h 1168;" dUSBD_EP5_FSTAT mx1hw.h 1163;" dUSBD_EP5_FWDP mx1hw.h 1169;" dUSBD_EP5_INTR mx1hw.h 1160;" dUSBD_EP5_LFRP mx1hw.h 1165;" dUSBD_EP5_LFWP mx1hw.h 1166;" dUSBD_EP5_MASK mx1hw.h 1161;" dUSBD_EP5_STAT mx1hw.h 1159;" dUSBD_FRAME mx1hw.h 1089;" dUSBD_INTR mx1hw.h 1095;" dUSBD_MASK mx1hw.h 1096;" dUSBD_MCTL mx1hw.h 1097;" dUSBD_SPEC mx1hw.h 1090;" dUSBD_STAT mx1hw.h 1091;" dUSER_EVENT0_DATA mx1hw.h 900;" dUSER_EVENT10_DATA mx1hw.h 910;" dUSER_EVENT11_DATA mx1hw.h 911;" dUSER_EVENT12_DATA mx1hw.h 912;" dUSER_EVENT13_DATA mx1hw.h 913;" dUSER_EVENT14_DATA mx1hw.h 914;" dUSER_EVENT15_DATA mx1hw.h 915;" dUSER_EVENT1_DATA mx1hw.h 901;" dUSER_EVENT2_DATA mx1hw.h 902;" dUSER_EVENT3_DATA mx1hw.h 903;" dUSER_EVENT4_DATA mx1hw.h 904;" dUSER_EVENT5_DATA mx1hw.h 905;" dUSER_EVENT6_DATA mx1hw.h 906;" dUSER_EVENT7_DATA mx1hw.h 907;" dUSER_EVENT8_DATA mx1hw.h 908;" dUSER_EVENT9_DATA mx1hw.h 909;" dUSR_STACK mx1hw.h 188;" dVBOOLEAN khead.h /^typedef volatile BOOLEAN VBOOLEAN;$/;" tVFLAG mx1hw.h 180;" dVOID khead.h /^typedef void VOID; \/* void *\/$/;" tVSINT16 khead.h /^typedef volatile SINT16 VSINT16;$/;" tVSINT32 khead.h /^typedef volatile SINT32 VSINT32;$/;" tVSINT8 khead.h /^typedef volatile SINT8 VSINT8;$/;" tVUINT16 khead.h /^typedef volatile UINT16 VUINT16;$/;" tVUINT32 khead.h /^typedef volatile UINT32 VUINT32;$/;" tVUINT8 khead.h /^typedef volatile UINT8 VUINT8;$/;" tWDOG_BASE_ADDR mx1hw.h 1189;" dWDOG_WCR mx1hw.h 1190;" dWDOG_WSR mx1hw.h 1191;" dWDOG_WSTR mx1hw.h 1192;" dZFLAG mx1hw.h 178;" d_CSI2C_H_ csi2c.h 2;" d_CSI_H_ csi.h 2;" d_I2C_H_ i2c.h 2;" d_IM8803_H_ im8803.h 2;" d_MYHEAD_H_ khead.h 2;" dbottom khead.h /^ POINT bottom; \/* Bottom right corner *\/$/;" m struct:capSeqNum csi2c.c /^static U32 capSeqNum;$/;" v file:cleanup_module csi2c.c /^void cleanup_module()$/;" fcsi2c_fops csi2c.c /^struct file_operations csi2c_fops = {$/;" vcsi2c_ioctl csi2c.c /^csi2c_ioctl(struct inode *inode, struct file *file,$/;" f file:csi2c_open csi2c.c /^static int csi2c_open(struct inode *inode, struct file *filp)$/;" f file:csi2c_read csi2c.c /^csi2c_read(struct file *filp, char *buf, size_t size, loff_t * l)$/;" f file:csi2c_release csi2c.c /^static int csi2c_release(struct inode *inode, struct file *filp)$/;" f file:csi2c_write csi2c.c /^csi2c_write(struct file *filp, const char *buf, size_t size, loff_t * l)$/;" f file:csi_data_buf csi2c.c /^static U32 *csi_data_buf = 0;$/;" v file:csi_intr_handler dma.c /^static void csi_intr_handler(int irq, void *dev_id, struct pt_regs *regs)$/;" f file:devfs_handle csi2c.c /^static devfs_handle_t devfs_handle;$/;" v file:dma_buf_phy_addr csi2c.c /^static U32 dma_buf_phy_addr;$/;" v file:dma_channel csi2c.c /^static dmach_t dma_channel;$/;" v file:dma_complete_handler dma.c /^static void dma_complete_handler()$/;" f file:dma_data_size csi2c.c /^static U32 dma_data_size;$/;" v file:dma_error_handler dma.c /^static void dma_error_handler(int error_type)$/;" f file:dprintcsi2c csi2c.h 7;" ddprintcsi2c csi2c.h 9;" ddprinti2cwr khead.h 100;" ddprinti2cwr khead.h 102;" deSRAM_8K_SIZE mx1hw.h 670;" deSRAM_ADDR_BOT mx1hw.h 665;" deSRAM_ADDR_LMT mx1hw.h 667;" deSRAM_ADDR_TOP mx1hw.h 666;" deSRAM_ASS_SIZE mx1hw.h 669;" deSRAM_PHY_SIZE mx1hw.h 668;" dfree_buffer dma.c /^static void free_buffer()$/;" f file:gMajor csi2c.c /^static int gMajor = 0;$/;" v file:init i2c.c /^static U32 init = 0;$/;" v file:init_module csi2c.c /^int init_module()$/;" fmalloc_buffer dma.c /^static int malloc_buffer()$/;" f file:port_init_I2C i2c.c /^static void port_init_I2C(void)$/;" f file:readSeqNum csi2c.c /^static U32 readSeqNum;$/;" v file:sensorFrameCount csi2c.c /^int sensorFrameCount = 0;$/;" vsensor_reset im8803.c /^void sensor_reset(void)$/;" fstandby_disable im8803.c /^void standby_disable(void)$/;" fstandby_enable im8803.c /^void standby_enable(void)$/;" fstopCMOScapture dma.c /^static void stopCMOScapture()$/;" f file:stopCapture csi2c.c /^static U8 stopCapture;$/;" v file:top khead.h /^ POINT top; \/* Top left corner *\/$/;" m struct:x khead.h /^ U16 x; \/* x point *\/$/;" m struct:y khead.h /^ U16 y; \/* y point *\/$/;" m struct:⌨️ 快捷键说明
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