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DMA_RTOR9 mx1hw.h 604;" dDMA_RTOSR mx1hw.h 505;" dDMA_SAR0 mx1hw.h 517;" dDMA_SAR1 mx1hw.h 526;" dDMA_SAR10 mx1hw.h 607;" dDMA_SAR2 mx1hw.h 535;" dDMA_SAR3 mx1hw.h 544;" dDMA_SAR4 mx1hw.h 553;" dDMA_SAR5 mx1hw.h 562;" dDMA_SAR6 mx1hw.h 571;" dDMA_SAR7 mx1hw.h 580;" dDMA_SAR8 mx1hw.h 589;" dDMA_SAR9 mx1hw.h 598;" dDMA_SYS_BASE mx1hw.h 486;" dDMA_TCR mx1hw.h 616;" dDMA_TDIPR mx1hw.h 619;" dDMA_TDRR mx1hw.h 618;" dDMA_TESR mx1hw.h 506;" dDMA_TFIFOA mx1hw.h 617;" dDMA_TFIFOB mx1hw.h 620;" dDMA_TST_BASE mx1hw.h 499;" dDMA_WSRA mx1hw.h 510;" dDMA_WSRB mx1hw.h 513;" dDMA_XSRA mx1hw.h 511;" dDMA_XSRB mx1hw.h 514;" dDMA_YSRA mx1hw.h 512;" dDMA_YSRB mx1hw.h 515;" dDMA_channel_disable dma_fun.c /^void DMA_channel_disable(U32 channel)$/;" fDMA_channel_enable dma_fun.c /^void DMA_channel_enable(U32 channel)$/;" fDMA_init dma_fun.c /^DMA_init(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest,$/;" fDMA_init1 dma_fun.c /^DMA_init1(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest, U32 Rpt)$/;" fDMA_init2 dma_fun.c /^DMA_init2(U32 Ch, U32 BurstLen, U32 Src, U32 ByteCount, U32 Dest,$/;" fDMA_init3 dma_fun.c /^void DMA_init3(U32 Ch, U32 BurstLen, U32 Src, U32 Dest, U32 Rpt)$/;" fDMA_init4 dma_fun.c /^void DMA_init4(U32 Ch, U32 BurstLen, U32 Src, U32 Dest, U32 Rpt)$/;" fDMA_module_enable dma_fun.c /^void DMA_module_enable(void)$/;" fDMA_module_reset dma_fun.c /^void DMA_module_reset(void)$/;" fDMA_poll dma_fun.c /^U32 DMA_poll(U32 channel)$/;" fDSPA_BASE_ADDR mx1hw.h 626;" dDSPA_DCTCTRL mx1hw.h 653;" dDSPA_DCTDESADD mx1hw.h 658;" dDSPA_DCTFIFO mx1hw.h 659;" dDSPA_DCTIRQENA mx1hw.h 655;" dDSPA_DCTIRQSTAT mx1hw.h 656;" dDSPA_DCTSRCADD mx1hw.h 657;" dDSPA_DCTVER mx1hw.h 654;" dDSPA_MAC_ACCU mx1hw.h 631;" dDSPA_MAC_BIT_SEL mx1hw.h 637;" dDSPA_MAC_BURST mx1hw.h 636;" dDSPA_MAC_CTRL mx1hw.h 629;" dDSPA_MAC_FIFO mx1hw.h 634;" dDSPA_MAC_FIFO_STAT mx1hw.h 635;" dDSPA_MAC_INTR mx1hw.h 632;" dDSPA_MAC_INTR_MASK mx1hw.h 633;" dDSPA_MAC_MOD mx1hw.h 628;" dDSPA_MAC_MULT mx1hw.h 630;" dDSPA_MAC_XBASE mx1hw.h 639;" dDSPA_MAC_XCOUNT mx1hw.h 644;" dDSPA_MAC_XINCR mx1hw.h 643;" dDSPA_MAC_XINDEX mx1hw.h 640;" dDSPA_MAC_XLENGTH mx1hw.h 641;" dDSPA_MAC_XMODIFY mx1hw.h 642;" dDSPA_MAC_YBASE mx1hw.h 646;" dDSPA_MAC_YCOUNT mx1hw.h 651;" dDSPA_MAC_YINCR mx1hw.h 650;" dDSPA_MAC_YINDEX mx1hw.h 647;" dDSPA_MAC_YLENGTH mx1hw.h 648;" dDSPA_MAC_YMODIFY mx1hw.h 649;" dEIM mx1hw.h 1211;" dEIM_BASE_ADDR mx1hw.h 1198;" dEIM_CS0H mx1hw.h 1199;" dEIM_CS0L mx1hw.h 1200;" dEIM_CS1H mx1hw.h 1201;" dEIM_CS1L mx1hw.h 1202;" dEIM_CS2H mx1hw.h 1203;" dEIM_CS2L mx1hw.h 1204;" dEIM_CS3H mx1hw.h 1205;" dEIM_CS3L mx1hw.h 1206;" dEIM_CS4H mx1hw.h 1207;" dEIM_CS4L mx1hw.h 1208;" dEIM_CS5H mx1hw.h 1209;" dEIM_CS5L mx1hw.h 1210;" dENABLE_FIQ mx1hw.h 169;" dENABLE_IRQ mx1hw.h 168;" dEVENT mx1hw.h 884;" dEVENT_PH mx1hw.h 883;" dEVENT_PORTHOLE mx1hw.h 882;" dEVENT_VALUE mx1hw.h 899;" dEXP_DATA_PH mx1hw.h 894;" dFAIL_PH mx1hw.h 888;" dFAIL_PORTHOLE mx1hw.h 887;" dFALSE khead.h 28;" dFBIT mx1hw.h 161;" dFINISH_PH mx1hw.h 892;" dFINISH_PORTHOLE mx1hw.h 891;" dFIPNDH mx1hw.h 283;" dFIPNDL mx1hw.h 284;" dFIQ_STACK mx1hw.h 187;" dFIVECSR mx1hw.h 276;" dFLAG_BITS mx1hw.h 176;" dGPCR mx1hw.h 1252;" dHEADERS Makefile /^HEADERS = mx1hw.h common.h myhead.h$/;" mI2C_BASE_ADDR mx1hw.h 810;" dI2C_CLKDIV i2c.h 5;" dI2C_I2CR mx1hw.h 813;" dI2C_I2DR mx1hw.h 815;" dI2C_I2SR mx1hw.h 814;" dI2C_IADR mx1hw.h 811;" dI2C_IFDR mx1hw.h 812;" dI2C_read i2c.c /^U32 I2C_read(U32 reg, U32 * _data)$/;" fI2C_test csi2c.c /^U32 I2C_test(void)$/;" fI2C_write i2c.c /^U32 I2C_write(U32 reg, U32 data)$/;" fIBIT mx1hw.h 162;" dIM8803_QQVGA_init im8803.c /^void IM8803_QQVGA_init(void)$/;" fIM8803_QVGA_init im8803.c /^void IM8803_QVGA_init(void)$/;" fIM8803_QVGA_init4 im8803.c /^void IM8803_QVGA_init4(void)$/;" fIM8803_VGA_init im8803.c /^void IM8803_VGA_init(void)$/;" fINTCNTL mx1hw.h 259;" dINTDISNUM mx1hw.h 262;" dINTENABLEH mx1hw.h 263;" dINTENABLEL mx1hw.h 264;" dINTENNUM mx1hw.h 261;" dINTERRUPT_BITS mx1hw.h 167;" dINTFRCH mx1hw.h 279;" dINTFRCL mx1hw.h 280;" dINTSRCH mx1hw.h 277;" dINTSRCL mx1hw.h 278;" dINTTYPEH mx1hw.h 265;" dINTTYPEL mx1hw.h 266;" dIOCTL_CSI_INIT csi2c.h 12;" dIOCTL_DMA_CAPTURE csi2c.h 19;" dIOCTL_I2C_READ csi2c.h 14;" dIOCTL_I2C_WRITE csi2c.h 13;" dIOCTL_INC_FRM csi2c.h 23;" dIOCTL_MOD_SATURATION csi2c.h 24;" dIOCTL_SET_GAIN csi2c.h 16;" dIOCTL_SET_INT_TIME csi2c.h 18;" dIOCTL_SET_VF_WIDTH csi2c.h 17;" dIOCTL_STOP_CAPTURE csi2c.h 22;" dIOCTL_SUBSAMPLE csi2c.h 15;" dIRQ_STACK mx1hw.h 186;" dLCDC_BASE_ADDR mx1hw.h 770;" dLCDC_PAL_ADDR mx1hw.h 771;" dLCDC_chcc mx1hw.h 777;" dLCDC_con mx1hw.h 778;" dLCDC_dma mx1hw.h 784;" dLCDC_gpm mx1hw.h 782;" dLCDC_hcc_w mx1hw.h 776;" dLCDC_hcc_xy mx1hw.h 775;" dLCDC_hsyn mx1hw.h 779;" dLCDC_int mx1hw.h 786;" dLCDC_pan mx1hw.h 781;" dLCDC_pwm mx1hw.h 783;" dLCDC_ram_0 mx1hw.h 788;" dLCDC_ram_1 mx1hw.h 789;" dLCDC_ram_2 mx1hw.h 790;" dLCDC_ram_3 mx1hw.h 791;" dLCDC_ram_4 mx1hw.h 792;" dLCDC_ram_5 mx1hw.h 793;" dLCDC_ram_6 mx1hw.h 794;" dLCDC_ram_7 mx1hw.h 795;" dLCDC_ram_8 mx1hw.h 796;" dLCDC_ram_9 mx1hw.h 797;" dLCDC_ram_a mx1hw.h 798;" dLCDC_ram_b mx1hw.h 799;" dLCDC_ram_c mx1hw.h 800;" dLCDC_ram_d mx1hw.h 801;" dLCDC_ram_e mx1hw.h 802;" dLCDC_ram_f mx1hw.h 803;" dLCDC_self mx1hw.h 785;" dLCDC_ssa mx1hw.h 772;" dLCDC_status mx1hw.h 787;" dLCDC_vpw mx1hw.h 774;" dLCDC_vsyn mx1hw.h 780;" dLCDC_xymax mx1hw.h 773;" dLD Makefile /^LD = arm-elf-linux-ld$/;" mLF mx1hw.h 1023;" dMCU_JNT_HALT mx1hw.h 916;" dMMC_ARGH mx1hw.h 851;" dMMC_ARGL mx1hw.h 852;" dMMC_BASE_ADDR mx1hw.h 839;" dMMC_BLK_LEN mx1hw.h 846;" dMMC_BUFFER_ACCESS mx1hw.h 854;" dMMC_BUF_PART_FULL mx1hw.h 855;" dMMC_CLK_RATE mx1hw.h 842;" dMMC_CMD mx1hw.h 850;" dMMC_CMD_DAT_CONT mx1hw.h 843;" dMMC_INT_MASK mx1hw.h 849;" dMMC_NOB mx1hw.h 847;" dMMC_OTHERS_REGS_1 mx1hw.h 856;" dMMC_OTHERS_REGS_2 mx1hw.h 857;" dMMC_OTHERS_REGS_3 mx1hw.h 858;" dMMC_OTHERS_REGS_4 mx1hw.h 859;" dMMC_OTHERS_REGS_5 mx1hw.h 860;" dMMC_OTHERS_REGS_6 mx1hw.h 861;" dMMC_READ_TO mx1hw.h 845;" dMMC_RESPONSE_TO mx1hw.h 844;" dMMC_RES_FIFO mx1hw.h 853;" dMMC_REV_NO mx1hw.h 848;" dMMC_STATUS mx1hw.h 841;" dMMC_STR_STP_CLK mx1hw.h 840;" dMODE_ABT mx1hw.h 156;" dMODE_BITS mx1hw.h 159;" dMODE_FIQ mx1hw.h 153;" dMODE_IRQ mx1hw.h 154;" dMODE_SVC mx1hw.h 155;" dMODE_SYS mx1hw.h 158;" dMODE_UND mx1hw.h 157;" dMODE_USR mx1hw.h 152;" dMSHC_BASE_ADDR mx1hw.h 867;" dMSHC_MSACMD mx1hw.h 874;" dMSHC_MSC2 mx1hw.h 873;" dMSHC_MSCLKD mx1hw.h 876;" dMSHC_MSCMD mx1hw.h 868;" dMSHC_MSCS mx1hw.h 869;" dMSHC_MSDATA mx1hw.h 870;" dMSHC_MSDRQC mx1hw.h 877;" dMSHC_MSFAECS mx1hw.h 875;" dMSHC_MSICS mx1hw.h 871;" dMSHC_MSPPCD mx1hw.h 872;" dMX1_DEF_INC mx1hw.h 46;" dNFLAG mx1hw.h 177;" dNIMASK mx1hw.h 260;" dNIPNDH mx1hw.h 281;" dNIPNDL mx1hw.h 282;" dNIPRIORITY0 mx1hw.h 274;" dNIPRIORITY1 mx1hw.h 273;" dNIPRIORITY2 mx1hw.h 272;" dNIPRIORITY3 mx1hw.h 271;" dNIPRIORITY4 mx1hw.h 270;" dNIPRIORITY5 mx1hw.h 269;" dNIPRIORITY6 mx1hw.h 268;" dNIPRIORITY7 mx1hw.h 267;" dNIVECSR mx1hw.h 275;" dPASS_PH mx1hw.h 886;" dPASS_PORTHOLE mx1hw.h 885;" dPCDR mx1hw.h 1253;" dPDEBUG khead.h 89;" dPDEBUG khead.h 93;" dPFUNC khead.h 90;" dPFUNC khead.h 94;" dPLINE khead.h 91;" dPLINE khead.h 95;" dPLL_BASE mx1hw.h 210;" dPLL_CSCR mx1hw.h 213;" dPLL_FMCR mx1hw.h 223;" dPLL_GPCR mx1hw.h 224;" dPLL_MCTL0 mx1hw.h 216;" dPLL_MCTL1 mx1hw.h 217;" dPLL_PCDR mx1hw.h 214;" dPLL_RSR mx1hw.h 221;" dPLL_SIDR mx1hw.h 222;" dPLL_UPCTL0 mx1hw.h 218;" dPLL_UPCTL1 mx1hw.h 219;" dPOINT khead.h /^} POINT, *P_POINT;$/;" tPTA_BASE_ADDR mx1hw.h 678;" dPTA_DDIR mx1hw.h 679;" dPTA_DR mx1hw.h 686;" dPTA_GIUS mx1hw.h 687;" dPTA_GPR mx1hw.h 693;" dPTA_ICONFA1 mx1hw.h 682;" dPTA_ICONFA2 mx1hw.h 683;" dPTA_ICONFB1 mx1hw.h 684;" dPTA_ICONFB2 mx1hw.h 685;" dPTA_ICR1 mx1hw.h 689;" dPTA_ICR2 mx1hw.h 690;" dPTA_IMR mx1hw.h 691;" dPTA_ISR mx1hw.h 692;" dPTA_OCR1 mx1hw.h 680;" dPTA_OCR2 mx1hw.h 681;" dPTA_PUEN mx1hw.h 695;" dPTA_SSR mx1hw.h 688;" dPTA_SWR mx1hw.h 694;" dPTB_BASE_ADDR mx1hw.h 701;" dPTB_DDIR mx1hw.h 702;" dPTB_DR mx1hw.h 709;" dPTB_GIUS mx1hw.h 710;" dPTB_GPR mx1hw.h 716;" dPTB_ICONFA1 mx1hw.h 705;" dPTB_ICONFA2 mx1hw.h 706;" dPTB_ICONFB1 mx1hw.h 707;" dPTB_ICONFB2 mx1hw.h 708;" dPTB_ICR1 mx1hw.h 712;" dPTB_ICR2 mx1hw.h 713;" dPTB_IMR mx1hw.h 714;" dPTB_ISR mx1hw.h 715;" dPTB_OCR1 mx1hw.h 703;" dPTB_OCR2 mx1hw.h 704;" dPTB_PUEN mx1hw.h 718;" dPTB_SSR mx1hw.h 711;" dPTB_SWR mx1hw.h 717;" dPTC_BASE_ADDR mx1hw.h 724;" dPTC_DDIR mx1hw.h 725;" dPTC_DR mx1hw.h 732;" dPTC_GIUS mx1hw.h 733;" dPTC_GPR mx1hw.h 739;" dPTC_ICONFA1 mx1hw.h 728;" dPTC_ICONFA2 mx1hw.h 729;" dPTC_ICONFB1 mx1hw.h 730;" dPTC_ICONFB2 mx1hw.h 731;" dPTC_ICR1 mx1hw.h 735;" dPTC_ICR2 mx1hw.h 736;" dPTC_IMR mx1hw.h 737;" dPTC_ISR mx1hw.h 738;" dPTC_OCR1 mx1hw.h 726;" dPTC_OCR2 mx1hw.h 727;" dPTC_PUEN mx1hw.h 741;" dPTC_SSR mx1hw.h 734;" dPTC_SWR mx1hw.h 740;" dPTD_BASE_ADDR mx1hw.h 747;" dPTD_DDIR mx1hw.h 748;" dPTD_DR mx1hw.h 755;" dPTD_GIUS mx1hw.h 756;" dPTD_GPR mx1hw.h 762;" dPTD_ICONFA1 mx1hw.h 751;" dPTD_ICONFA2 mx1hw.h 752;" dPTD_ICONFB1 mx1hw.h 753;" dPTD_ICONFB2 mx1hw.h 754;" dPTD_ICR1 mx1hw.h 758;" dPTD_ICR2 mx1hw.h 759;" dPTD_IMR mx1hw.h 760;" dPTD_ISR mx1hw.h 761;" dPTD_OCR1 mx1hw.h 749;" dPTD_OCR2 mx1hw.h 750;" dPTD_PUEN mx1hw.h 764;" dPTD_SSR mx1hw.h 757;" d⌨️ 快捷键说明
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