📄 lib_at91rm3400.h
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//*----------------------------------------------------------------------------
//* \fn AT91F_US2_CfgPIO
//* \brief Configure PIO controllers to drive US2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PIN42_TXD2) |
((unsigned int) AT91C_PIN41_RXD2), // Peripheral A
((unsigned int) AT91C_PIN50_CTS2) |
((unsigned int) AT91C_PIN47_RTS2)); // Peripheral B
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN55_RTS2)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPMC
//* \brief Enable Peripheral clock in PMC for US1
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US1_CfgPIO
//* \brief Configure PIO controllers to drive US1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PIN39_DCD1) |
((unsigned int) AT91C_PIN37_DTR1) |
((unsigned int) AT91C_PIN31_RXD1) |
((unsigned int) AT91C_PIN32_TXD1) |
((unsigned int) AT91C_PIN33_RTS1) |
((unsigned int) AT91C_PIN38_DSR1) |
((unsigned int) AT91C_PIN40_RI1) |
((unsigned int) AT91C_PIN34_CTS1), // Peripheral A
((unsigned int) AT91C_PIN44_RTS1)); // Peripheral B
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN75_DTR1)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPMC
//* \brief Enable Peripheral clock in PMC for US0
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_US0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_US0_CfgPIO
//* \brief Configure PIO controllers to drive US0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_US0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PIN25_RXD0) |
((unsigned int) AT91C_PIN24_TXD0) |
((unsigned int) AT91C_PIN26_SCK0) |
((unsigned int) AT91C_PIN28_RTS0) |
((unsigned int) AT91C_PIN27_CTS0), // Peripheral A
((unsigned int) AT91C_PIN43_RTS0)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_CfgPMC
//* \brief Enable Peripheral clock in PMC for UDP
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_UDP));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_UDP_CfgPIO
//* \brief Configure PIO controllers to drive UDP signals
//*----------------------------------------------------------------------------
__inline void AT91F_UDP_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN46_UEON) |
((unsigned int) AT91C_PIN41_URXD) |
((unsigned int) AT91C_PIN19_USUSPEND) |
((unsigned int) AT91C_PIN25_UTXOEN) |
((unsigned int) AT91C_PIN42_UTXD)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPMC
//* \brief Enable Peripheral clock in PMC for AIC
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_IRQ4) |
((unsigned int) 1 << AT91C_ID_FIQ) |
((unsigned int) 1 << AT91C_ID_IRQ5) |
((unsigned int) 1 << AT91C_ID_IRQ6) |
((unsigned int) 1 << AT91C_ID_IRQ0) |
((unsigned int) 1 << AT91C_ID_IRQ1) |
((unsigned int) 1 << AT91C_ID_IRQ2) |
((unsigned int) 1 << AT91C_ID_IRQ3));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_AIC_CfgPIO
//* \brief Configure PIO controllers to drive AIC signals
//*----------------------------------------------------------------------------
__inline void AT91F_AIC_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
((unsigned int) AT91C_PIN90_IRQ0) |
((unsigned int) AT91C_PIN91_IRQ1) |
((unsigned int) AT91C_PIN92_IRQ2) |
((unsigned int) AT91C_PIN93_IRQ3) |
((unsigned int) AT91C_PIN94_IRQ4) |
((unsigned int) AT91C_PIN95_IRQ5) |
((unsigned int) AT91C_PIN96_IRQ6) |
((unsigned int) AT91C_PIN89_FIQ), // Peripheral A
0); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC6_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC6
//*----------------------------------------------------------------------------
__inline void AT91F_TC6_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC5));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC6_CfgPIO
//* \brief Configure PIO controllers to drive TC6 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC6_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN65_TIOB5) |
((unsigned int) AT91C_PIN68_TCLK5) |
((unsigned int) AT91C_PIN72_TIOA5)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC5_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC5
//*----------------------------------------------------------------------------
__inline void AT91F_TC5_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC4));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC5_CfgPIO
//* \brief Configure PIO controllers to drive TC5 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC5_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN59_TIOB4) |
((unsigned int) AT91C_PIN60_TCLK4) |
((unsigned int) AT91C_PIN64_TIOA4)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC4_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC4
//*----------------------------------------------------------------------------
__inline void AT91F_TC4_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC3));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC4_CfgPIO
//* \brief Configure PIO controllers to drive TC4 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC4_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOB, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN54_TCLK3) |
((unsigned int) AT91C_PIN58_TIOA3) |
((unsigned int) AT91C_PIN53_TIOB3)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC2
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC2));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC2_CfgPIO
//* \brief Configure PIO controllers to drive TC2 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC2_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN39_TIOA2) |
((unsigned int) AT91C_PIN27_TCLK1) |
((unsigned int) AT91C_PIN40_TIOB2) |
((unsigned int) AT91C_PIN28_TCLK2)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC1
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC1));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC1_CfgPIO
//* \brief Configure PIO controllers to drive TC1 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC1_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN37_TIOA1) |
((unsigned int) AT91C_PIN38_TIOB1)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPMC
//* \brief Enable Peripheral clock in PMC for TC0
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_TC0));
}
//*----------------------------------------------------------------------------
//* \fn AT91F_TC0_CfgPIO
//* \brief Configure PIO controllers to drive TC0 signals
//*----------------------------------------------------------------------------
__inline void AT91F_TC0_CfgPIO (void)
{
// Configure PIO controllers to periph mode
AT91F_PIO_CfgPeriph(
AT91C_BASE_PIOA, // PIO controller base address
0, // Peripheral A
((unsigned int) AT91C_PIN33_TIOA0) |
((unsigned int) AT91C_PIN34_TIOB0)); // Peripheral B
}
//*----------------------------------------------------------------------------
//* \fn AT91F_ST_CfgPMC
//* \brief Enable Peripheral clock in PMC for ST
//*----------------------------------------------------------------------------
__inline void AT91F_ST_CfgPMC (void)
{
AT91F_PMC_EnablePeriphClock(
AT91C_BASE_PMC, // PIO controller base address
((unsigned int) 1 << AT91C_ID_SYS));
}
#endif // lib_AT91RM3400_H
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