📄 at91rm3400.h
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// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Management Controler
// *****************************************************************************
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved0[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved1[5]; //
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved2[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
} AT91S_PMC, *AT91PS_PMC;
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock
#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output
#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected
#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64
#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division
#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same
#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock
#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Clock Generator Controler
// *****************************************************************************
typedef struct _AT91S_CKGR {
AT91_REG CKGR_MOR; // Main Oscillator Register
AT91_REG CKGR_MCFR; // Main Clock Frequency Register
AT91_REG CKGR_PLLAR; // PLL A Register
AT91_REG CKGR_PLLBR; // PLL B Register
} AT91S_CKGR, *AT91PS_CKGR;
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time
// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter
#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range
#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier
#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source
// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected
#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0
#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter
#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range
#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
AT91_REG Reserved3[1]; //
AT91_REG PIO_PPUDR; // Pull-up Disable Register
AT91_REG PIO_PPUER; // Pull-up Enable Register
AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
AT91_REG Reserved4[1]; //
AT91_REG PIO_ASR; // Select A Register
AT91_REG PIO_BSR; // Select B Register
AT91_REG PIO_ABSR; // AB Select Status Register
AT91_REG Reserved5[9]; //
AT91_REG PIO_OWER; // Output Write Enable Register
AT91_REG PIO_OWDR; // Output Write Disable Register
AT91_REG PIO_OWSR; // Output Write Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Debug Unit
// *****************************************************************************
typedef struct _AT91S_DBGU {
AT91_REG DBGU_CR; // Control Register
AT91_REG DBGU_MR; // Mode Register
AT91_REG DBGU_IER; // Interrupt Enable Register
AT91_REG DBGU_IDR; // Interrupt Disable Register
AT91_REG DBGU_IMR; // Interrupt Mask Register
AT91_REG DBGU_CSR; // Channel Status Register
AT91_REG DBGU_RHR; // Receiver Holding Register
AT91_REG DBGU_THR; // Transmitter Holding Register
AT91_REG DBGU_BRGR; // Baud Rate Generator Register
AT91_REG Reserved0[7]; //
AT91_REG DBGU_C1R; // Chip ID1 Register
AT91_REG DBGU_C2R; // Chip ID2 Register
AT91_REG DBGU_FNTR; // Force NTRST Register
AT91_REG Reserved1[45]; //
AT91_REG DBGU_RPR; // Receive Pointer Register
AT91_REG DBGU_RCR; // Receive Counter Register
AT91_REG DBGU_TPR; // Transmit Pointer Register
AT91_REG DBGU_TCR; // Transmit Counter Register
AT91_REG DBGU_RNPR; // Receive Next Pointer Register
AT91_REG DBGU_RNCR; // Receive Next Counter Register
AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
AT91_REG DBGU_TNCR; // Transmit Next Counter Register
AT91_REG DBGU_PTCR; // PDC Transfer Control Register
AT91_REG DBGU_PTSR; // PDC Transfer Status Register
} AT91S_DBGU, *AT91PS_DBGU;
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