📄 apmc.h
字号:
//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : apmcBooster.h
//* Object : Power Management Controller Header File.
//*
//* 1.0 13/02/01 HI : Creation
//* 1.1 26/11/01 HI : PLLS output ranges modification and add APMC_USB_96M
//*----------------------------------------------------------------------------
#ifndef apmcBooster_h
#define apmcBooster_h
#include "periph/stdc/std_c.h"
/*---------------------------------------*/
/* Advanced Power Management Controller */
/*---------------------------------------*/
typedef struct _AT91S_APMC
{
at91_reg APMC_SCER ; /* System Clock Enable Register */
at91_reg APMC_SCDR ; /* System Clock Disable Register */
at91_reg APMC_SCSR ; /* System Clock Status Register */
at91_reg Reserved0 ;
at91_reg APMC_PCER ; /* Peripheral Clock Enable Register */
at91_reg APMC_PCDR ; /* Peripheral Clock Disable Register */
at91_reg APMC_PCSR ; /* Peripheral Clock Status Register */
at91_reg Reserved1 ;
at91_reg APMC_MOR ; /* Main Oscillator Register */
at91_reg APMC_MCFR ; /* Main clock Frequency Register */
at91_reg APMC_PLLAR ; /* PLLA Register */
at91_reg APMC_PLLBR ; /* PLLB Register */
at91_reg APMC_MCKR ; /* Master Clock Register */
at91_reg Reserved2 ;
at91_reg Reserved3 ;
at91_reg Reserved4 ;
at91_reg APMC_PCKR[8]; /* Pad[0..7] clock Register */
at91_reg APMC_IER ; /* Interrupt Enable Register */
at91_reg APMC_IDR ; /* Interrupt Disable Register */
at91_reg APMC_SR ; /* Status Register */
at91_reg APMC_IMR ; /* Interrupt Mask Register 6C*/
// at91_reg reserved5[(0x80-0x70)];
at91_reg reserved5;
at91_reg reserved6;
at91_reg reserved7;
at91_reg reserved8;
at91_reg reserved9 ; /* PLLs Factors0 Register */
} AT91S_APMC, *AT91PS_APMC ;
/*------------------------------------------------------*/
/* APMC Registers Bits Definition SCER,SCDR,SCSR */
/*------------------------------------------------------*/
#define APMC_PROC 0x1 /* CPU Clock enabled */
#define APMC_UDP 0x2 /* 48MHZ USB Clock enabled */
#define APMC_PCK0 0x100 /* Pad0 Clock enabled */
#define APMC_PCK1 0x200 /* Pad0 Clock enabled */
#define APMC_PCK2 0x400 /* Pad0 Clock enabled */
#define APMC_PCK3 0x800 /* Pad0 Clock enabled */
#define APMC_PCK4 0x1000 /* Pad0 Clock enabled */
#define APMC_PCK5 0x2000 /* Pad0 Clock enabled */
#define APMC_PCK6 0x4000 /* Pad0 Clock enabled */
#define APMC_PCK7 0x8000 /* Pad0 Clock enabled */
/*------------------------------------------------------*/
/* APMC Registers Bits Definition PCER,PCDR,PCSR */
/*------------------------------------------------------*/
#define APMC_SYSTEM_CLOCK 0x02
#define APMC_SSC0 0x04 /* SSC0 Clock enabled */
#define APMC_SSC1 0x08 /* SSC1 Clock enabled */
#define APMC_SSC2 0x10 /* SSC2 Clock enabled */
#define APMC_US0 0x20 /* US0 Clock enabled */
#define APMC_US1 0x40 /* US1 Clock enabled */
#define APMC_US2 0x80 /* US2 Clock enabled */
#define APMC_US3 0x100 /* US3 Clock enabled */
#define APMC_SPI0 0x200 /* SPI0 Clock enabled */
#define APMC_SPI1 0x400 /* SPI1 Clock enabled */
#define APMC_TC0 0x800 /* TC0 Clock enabled */
#define APMC_TC1 0x1000 /* TC1 Clock enabled */
#define APMC_TC2 0x2000 /* TC2 Clock enabled */
#define APMC_TC3 0x4000 /* TC3 Clock enabled */
#define APMC_TC4 0x8000 /* TC4 Clock enabled */
#define APMC_TC5 0x10000 /* TC5 Clock enabled */
#define APMC_PIO0 0x20000 /* PIO0 Clock enabled */
#define APMC_PIO1 0x40000 /* PIO1 Clock enabled */
#define APMC_DAC 0x80000 /* DAC Clock enabled */
#define APMC_ADC0 0x100000 /* ADC0 Clock enabled */
#define APMC_ADC1 0x200000 /* ADC1 Clock enabled */
#define APMC_ADC2 0x400000 /* ADC2 Clock enabled */
#define APMC_ADC3 0x800000 /* ADC3 Clock enabled */
#define APMC_USB_CLK 0x1000000 /* USB Clock enabled */
/*------------------------------------------------------*/
/* APMC Main Oscillator Register MOR */
/*------------------------------------------------------*/
#define APMC_MOSCEN 0x1 /* Main oscillator enabled */
/*------------------------------------------------------*/
/* APMC Frequency Main Register MCFR */
/*------------------------------------------------------*/
#define APMC_FREQ_END 0x10000 /* Frequency measurement ended : the main frequency is stable*/
/*------------------------------------------------------*/
/* APMC PLL Registers Bits Definition PPLAR, PLLBR */
/*------------------------------------------------------*/
#define APMC_DIVIDER_NONE 0x0 /* No divider */
#define APMC_DIVIDER_INPUT 0x1 /* Divider output is divider input */
#define APMC_CLK_RANGE_80_TO_160MHZ 0 /* Frequency range output 80 Mhz to 160 Mhz */
#define APMC_CLK_RANGE_150_TO_240MHZ 0x8000 /* Frequency range output 150 Mhz to 240 Mhz */
#define APMC_CLK_RANGE_20_TO_70MHZ 0 /* Frequency range output 20 Mhz to 70 Mhz */
#define APMC_CLK_RANGE_70_TO_100MHZ 0x8000 /* Frequency range output 70 Mhz to 100 Mhz */
#define APMC_USB_96M (1 << 28)/* if set a divider by 2 is inserted between the pllb output(96 MHz) and the usb clock(48 Mhz) */
#define APMC_USB_PLL (1 << 29)
/*------------------------------------------------------*/
/* APMC Master clock Register Bits Definition MCKR */
/*------------------------------------------------------*/
#define APMC_MCKS_32K 0x0 /* Selection clock 32K */
#define APMC_MCKS_MAIN 0x1 /* Selection clock Main */
#define APMC_MCKS_PLLA 0x2 /* Selection clock from PLLA */
#define APMC_MCKS_PLLB 0x3 /* Selection clock from PLLB */
#define APMC_DIVMCK_NONE 0 /* No divider */
#define APMC_DIVMCK_DIV2 0x04 /* Selected Clock Divided by 2 */
#define APMC_DIVMCK_DIV4 0x08 /* Selected Clock Divided by 4 */
#define APMC_DIVMCK_DIV8 0x0C /* Selected Clock Divided by 8 */
#define APMC_DIVMCK_DIV16 0x10 /* Selected Clock Divided by 16 */
#define APMC_DIVMCK_DIV32 0x14 /* Selected Clock Divided by 32 */
#define APMC_DIVMCK_DIV64 0x18 /* Selected Clock Divided by 64 */
/*------------------------------------------------------*/
/* APMC Pad clock Register Bits Definition PCK0..PCK7 */
/*------------------------------------------------------*/
#define APMC_PCKS_32K 0x0 /* Selection clock 32K */
#define APMC_PCKS_MAIN 0x1 /* Selection clock Main */
#define APMC_PCKS_PLLA 0x2 /* Selection clock from PLLA */
#define APMC_PCKS_PLLB 0x3 /* Selection clock from PLLB */
#define APMC_DIVPCK_NONE 0x0 /* No divider */
#define APMC_DIVPCK_DIV2 0x04 /* Selected Clock Divided by 2 */
#define APMC_DIVPCK_DIV4 0x08 /* Selected Clock Divided by 4 */
#define APMC_DIVPCK_DIV8 0x0C /* Selected Clock Divided by 8 */
#define APMC_DIVPCK_DIV16 0x10 /* Selected Clock Divided by 16 */
#define APMC_DIVPCK_DIV32 0x14 /* Selected Clock Divided by 32 */
#define APMC_DIVPCK_DIV64 0x18 /* Selected Clock Divided by 64 */
/*------------------------------------------------------*/
/* APM SR, IER, IDR and IMR Registers Bits Definition */
/*------------------------------------------------------*/
#define APMC_MOSCS 0x1 /* Main Ready Flag */
#define APMC_LOCKA 0x2 /* PLLA Ready Flag */
#define APMC_LOCKB 0x4 /* PLLB Ready Flag */
#define APMC_MCK_RDY 0x8 /* MCK Ready Flag */
#define APMC_PCK0_RDY 0x100 /* PCK0 Ready Flag */
#define APMC_PCK1_RDY 0x200 /* PCK1 Ready Flag */
#define APMC_PCK2_RDY 0x400 /* PCK2 Ready Flag */
#define APMC_PCK3_RDY 0x800 /* PCK3 Ready Flag */
#define APMC_PCK4_RDY 0x1000 /* PCK4 Ready Flag */
#define APMC_PCK5_RDY 0x2000 /* PCK5 Ready Flag */
#define APMC_PCK6_RDY 0x4000 /* PCK6 Ready Flag */
#define APMC_PCK7_RDY 0x8000 /* PCK7 Ready Flag */
#endif //* apmcBooster_h
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -