apmc.inc

ARM9200开发板的ROM boot程序源码1.0

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File Name            : apmcbooster.inc
;- Object               : Assembler Power Management Controller Definition File.
;-
;- 1.0 04/04/01  HI     : Creation
;------------------------------------------------------------------------------

;--------------------------------------------------------------------------
;- Advanced Power Management Controller User Interface Structure Definition
;--------------------------------------------------------------------------
                ^       0
APMC_SCER       #       4       ;- Source Clock Enable Register
APMC_SCDR 	#       4	;- System Clock Disable Register 
APMC_SCSR   	#       4	;- System Clock Status  Register 
Reserved0 	#       4

APMC_PCER   	#       4	;- Peripheral Clock Enable  Register 
APMC_PCDR   	#       4	;- Peripheral Clock Disable Register 
APMC_PCSR   	#       4	;- Peripheral Clock Status  Register 
Reserved1 	#       4

APMC_MOR 	#       4	;- Main Oscillator Register 
APMC_MCFR 	#       4	;- Main clock frequency Register 
APMC_PLLAR	#       4  	;- PLLA Register 
APMC_PLLBR 	#       4  	;- PLLB Register 

APMC_MCKR 	#       4  	;- Master Clock Register 
Reserved2 	#       4
Reserved3 	#       4
Reserved4 	#       4

APMC_PCKR  	#       8*4	;- Pad[0..7] Registers
	
APMC_IER 	#       4  	;- Interrupt Enable Register 
APMC_IDR 	#       4  	;- Interrupt Disable Register 
APMC_SR 	#       4  	;- Status Register 
APMC_IMR 	#       4  	;- Interrupt Mask Register 

reserved5       #       4	;- Reserved
reserved6       #       4	;- Reserved
reserved7       #       4	;- Reserved
reserved8       #       4	;- Reserved
	
reserved9   	#       4	;- Reserved

;-------------------------------------------------------
;- APM Clock Registers Bits Definition                  
;-------------------------------------------------------
APMC_PROC	EQU	0x1		;- CPU  Clock enabled 
APMC_UDP	EQU	0x2		;- 48MHZ USB Clock enabled 
APMC_PCK0	EQU	0x100		;- Pad0 Clock enabled 
APMC_PCK1	EQU	0x200		;- Pad0 Clock enabled 
APMC_PCK2	EQU	0x400		;- Pad0 Clock enabled 
APMC_PCK3	EQU	0x800		;- Pad0 Clock enabled 
APMC_PCK4	EQU	0x1000		;- Pad0 Clock enabled 
APMC_PCK5	EQU	0x2000		;- Pad0 Clock enabled 
APMC_PCK6	EQU	0x4000		;- Pad0 Clock enabled 
APMC_PCK7	EQU	0x8000		;- Pad0 Clock enabled 


;-------------------------------------------------------
;- APM Main Oscillator Register Bits Definition         
;-------------------------------------------------------
APMC_MOSCEN	EQU	0x1		;- Main oscillator enabled 

APMC_SYSTEM_CLOCK EQU	0x02

;-------------------------------------------------------
;- APM PLL Registers Bits Definition                    
;-------------------------------------------------------
APMC_DIVIDER_NONE		EQU	0x0	;- No divider 
APMC_DIVIDER_INPUT		EQU	0x1	;- Divider output is divider input 
 
APMC_CLK_RANGE_40_TO_250MHZ 	EQU	0x0000	;- Frequency range output 40 Mhz to 250 Mhz 	
APMC_CLK_RANGE_20_TO_40MHZ  	EQU	0x4000 	;- Frequency range output 20 Mhz to 40 Mhz 	
APMC_CLK_RANGE_10_TO_20MHZ  	EQU	0x8000	;- Frequency range output 10 Mhz to 20 Mhz 	
APMC_CLK_RANGE_5_TO_10MHZ   	EQU	0xC000	;- Frequency range output 5 Mhz to 10 Mhz 	

APCM_USB_PLL			EQU	0x20000000 	;- PLL used for USB 
APMC_PLL_TEST			EQU	0x40000000 	;- PLL Test enabled 
APMC_PLL_EN			EQU	0x80000000 	;- PLL enabled 

APMC_PLL_MULT_FACTOR_SHIFT	EQU	16
APMC_CLK_RANGE_OUT_SHIFT	EQU	14
APMC_PLL_STARTUP_MAX_SHIFT	EQU	8
 
;-------------------------------------------------------
;- APM Master Register Bits Definition                  
;-------------------------------------------------------
APMC_MCK			EQU	0x0
APMC_MCKS_32K			EQU	0x0	;- Selection clock 32K 
APMC_MCKS_MAIN			EQU	0x1	;- Selection clock Main 
APMC_MCKS_PLLA			EQU	0x2	;- Selection clock from PLLA 
APMC_MCKS_PLLB			EQU	0x3	;- Selection clock from PLLB 

APMC_DIVMCK_NONE		EQU	0x0	;- No divider 
APMC_DIVMCK_DIV2		EQU	0x04	;- Selected Clock Divided by 2 
APMC_DIVMCK_DIV4		EQU	0x08	;- Selected Clock Divided by 4 
APMC_DIVMCK_DIV8		EQU	0x0C	;- Selected Clock Divided by 8 
APMC_DIVMCK_DIV16		EQU	0x10	;- Selected Clock Divided by 16 
APMC_DIVMCK_DIV32		EQU	0x14	;- Selected Clock Divided by 32 
APMC_DIVMCK_DIV64		EQU	0x18	;- Selected Clock Divided by 64 

APMC_DIVMCK_SHIFT		EQU	2

;-------------------------------------------------------
;- APM Pad Registers Bits Definition                    
;-------------------------------------------------------
APMC_PCKS_32K			EQU	0x0	;- Selection clock 32K 
APMC_PCKS_MAIN			EQU	0x1	;- Selection clock Main 
APMC_PCKS_PLLA			EQU	0x2	;- Selection clock from PLLA 
APMC_PCKS_PLLB			EQU	0x3	;- Selection clock from PLLB 

APMC_DIVPCK_NONE		EQU	0x0	;- No divider 
APMC_DIVPCK_DIV2		EQU	0x04	;- Selected Clock Divided by 2 
APMC_DIVPCK_DIV4		EQU	0x08	;- Selected Clock Divided by 4 
APMC_DIVPCK_DIV8		EQU	0x0C	;- Selected Clock Divided by 8 
APMC_DIVPCK_DIV16		EQU	0x10	;- Selected Clock Divided by 16 
APMC_DIVPCK_DIV32		EQU	0x14	;- Selected Clock Divided by 32 
APMC_DIVPCK_DIV64		EQU	0x18	;- Selected Clock Divided by 64 



;-------------------------------------------------------
;- APM SR, IER, IDR and IMR Registers Bits Definition   
;-------------------------------------------------------
APMC_MAIN_RDY			EQU	0x1	;- Main Ready Flag 
APMC_PLLA_RDY			EQU	0x2	;- PLLA Ready Flag 
APMC_PLLB_RDY			EQU	0x4	;- PLLB Ready Flag 
APMC_MCK_RDY			EQU	0x8	;- MCK  Ready Flag 
APMC_PCK0_RDY			EQU	0x100	;- PCK0 Ready Flag 
APMC_PCK1_RDY			EQU	0x200	;- PCK1 Ready Flag 
APMC_PCK2_RDY			EQU	0x400	;- PCK2 Ready Flag 
APMC_PCK3_RDY			EQU	0x800	;- PCK3 Ready Flag 
APMC_PCK4_RDY			EQU	0x1000	;- PCK4 Ready Flag 
APMC_PCK5_RDY			EQU	0x2000	;- PCK5 Ready Flag 
APMC_PCK6_RDY			EQU	0x4000	;- PCK6 Ready Flag 
APMC_PCK7_RDY			EQU	0x8000	;- PCK7 Ready Flag 

;-------------------------------------------------------
;- APM PLLs Factors Registers Bits Definition           
;-------------------------------------------------------
APMC_PLLA_VALUE                 EQU     0x03E80000:OR:APMC_CLK_RANGE_20_TO_40MHZ:OR:0x00003F00:OR:APMC_DIVIDER_INPUT
;APMC_MCKR_VALUE                 EQU     APMC_MCKS_PLLA
APMC_MCKR_VALUE                 EQU     APMC_MCKS_32K
 
 
            END