cachec.inc

ARM9200开发板的ROM boot程序源码1.0

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File Name            : cachec.inc
;- Object               : Assembler CACHE Definition File.
;-
;- 1.0 19/01/01 ED      : Creation
;------------------------------------------------------------------------------

BAD_ID_CODE		EQU	0xF		;- Bad Register Identifier

;--------------------------------------------------------
;- ID Register Code Definition (Register 0: c0)
;--------------------------------------------------------

CACHE_ID		EQU	0x0		;- Cache ID Register Identifier

CACHE_2KB		EQU	0xFF1C7400	;- 2KB Cache variant identifier
CACHE_4KB		EQU	0xFF2C7400	;- 4KB Cache variant identifier
CACHE_8KB		EQU	0xFF3C7400	;- 8KB Cache variant identifier
CACHE_16KB		EQU	0xFF4C7400	;- 16KB Cache variant identifier

CACHE_VERSION_MASK	EQU	0x0000000F	;- Cache Version Mask

;--------------------------------------------------------
;- Control Register Definition (Register 1: c1)
;--------------------------------------------------------

CACHE_CR		EQU	0x1		;- Cache CR Register Identifier

CACHE_DIS		EQU	0x0		;- Cache disabled

CACHE_PROTDIS_MASK	EQU	0xFFFFFFFE	;- On-chip protection unit disabled mask
CACHE_PROTEN		EQU	0x1		;- On-chip protection unit enabled
CACHE_DIS_MASK		EQU	0xFFFFFFFB	;- Cache disabled mask
CACHE_EN		EQU	0x4		;- Cache enabled

CACHE_SPLIT_MODE	EQU	0x1000000	;- Split Instruction/Data Mode control bit
SPLIT_1INS_3DATA	EQU	0x2000000	;- 1 Bank Instruction, 3 Banks Data
SPLIT_2INS_2DATA	EQU	0x4000000	;- 2 Bank Instruction, 2 Banks Data
SPLIT_3INS_1DATA	EQU	0x6000000	;- 3 Bank Instruction, 1 Banks Data

CACHE_LOAD_MODE		EQU	0x8000000	;- Partially-locked Operation control bit
LOCK_0BANK		EQU	0x0		;- No Banks Locked
LOCK_1BANK		EQU	0x2000000	;- 1 Bank Locked
LOCK_2BANK		EQU	0x4000000	;- 2 Bank Locked
LOCK_3BANK		EQU	0x6000000	;- 3 Bank Locked
UNLOCK_ALL_MASK		EQU	0xF9FFFFFF	;- All Banks unlocked
CACHE_BANK0_MASK	EQU	0xCFFFFFFF	;- 0 Cache Banks Mask

CACHE_BANK0		EQU	0x0		;- Bank 0
CACHE_BANK1		EQU	0x10000000	;- Bank 1
CACHE_BANK2		EQU	0x20000000	;- Bank 2
CACHE_BANK3		EQU	0x30000000	;- Bank 3

;--------------------------------------------------------
;- Cacheable Register Definition (Register 2: c2)
;--------------------------------------------------------

CACHE_CA		EQU	0x2		;- Cache CA Register Identifier

CACHE_AREADIS		EQU	0x0		;- Area defined Uncacheable

CACHE_AREA0EN		EQU	0x1		;- Area 0 defined Cacheable
CACHE_AREA1EN		EQU	0x2		;- Area 1 defined Cacheable
CACHE_AREA2EN		EQU	0x4		;- Area 2 defined Cacheable
CACHE_AREA3EN		EQU	0x8		;- Area 3 defined Cacheable
CACHE_AREA4EN		EQU	0x10		;- Area 4 defined Cacheable
CACHE_AREA5EN		EQU	0x20		;- Area 5 defined Cacheable
CACHE_AREA6EN		EQU	0x40		;- Area 6 defined Cacheable
CACHE_AREA7EN		EQU	0x80		;- Area 8 defined Cacheable

CACHE_AREA0DIS_MASK	EQU	0xFFFFFFFE	;- Area 0 defined Uncacheable mask
CACHE_AREA1DIS_MASK	EQU	0xFFFFFFFD	;- Area 1 defined Uncacheable mask
CACHE_AREA2DIS_MASK	EQU	0xFFFFFFFB	;- Area 2 defined Uncacheable mask
CACHE_AREA3DIS_MASK	EQU	0xFFFFFFF7	;- Area 3 defined Uncacheable mask
CACHE_AREA4DIS_MASK	EQU	0xFFFFFFEF	;- Area 4 defined Uncacheable mask
CACHE_AREA5DIS_MASK	EQU	0xFFFFFFDF	;- Area 5 defined Uncacheable mask
CACHE_AREA6DIS_MASK	EQU	0xFFFFFFBF	;- Area 6 defined Uncacheable mask
CACHE_AREA7DIS_MASK	EQU	0xFFFFFF7F	;- Area 7 defined Uncacheable mask

;--------------------------------------------------------
;- Protection Register Definition (Register 5: c5)
;--------------------------------------------------------

CACHE_PR		EQU	0x5		;- Cache PR Register Identifier

CACHE_PROT_EN_MASK	EQU	0x3		;- Area Protection enable Mask

CACHE_AREA_NOACC	EQU	0x0		;- No Access to the Area in any Mode
CACHE_AREA_RWSUP	EQU	0x1		;- R/W Access in Supervisor Mode
						;- No Access in User Mode
CACHE_AREA_RWSUP_ROUS	EQU	0x2		;- R/W Access in Supervisor Mode
						;- Read-only Access in User Mode
CACHE_AREA_RWALL	EQU	0x3		;- R/W Access to the Area in any Mode

CACHE_AREA0MODE		EQU	0x0		;- Area 0 Protection Definition bits
CACHE_AREA1MODE		EQU	0x2		;- Area 1 Protection Definition bits
CACHE_AREA2MODE		EQU	0x4		;- Area 2 Protection Definition bits
CACHE_AREA3MODE		EQU	0x6		;- Area 3 Protection Definition bits
CACHE_AREA4MODE		EQU	0x8		;- Area 4 Protection Definition bits
CACHE_AREA5MODE		EQU	0xA		;- Area 5 Protection Definition bits
CACHE_AREA6MODE		EQU	0xC		;- Area 6 Protection Definition bits
CACHE_AREA7MODE		EQU	0xE		;- Area 7 Protection Definition bits

;--------------------------------------------------------
;- Memory Area Register Definition (Register 6: c6)
;--------------------------------------------------------

CACHE_MR		EQU	0x6		;- Cache MR Register Identifier

AREA_DIS		EQU	0x0		;- Area disabled

AREA_DIS_MASK		EQU	0xFFFFFFFE	;- Area disable mask
AREA_EN			EQU	0x1		;- Area enabled

AREA_4KB		EQU	0x16		;- Area Size = 4KB
AREA_8KB		EQU	0x18		;- Area Size = 8KB
AREA_16KB		EQU	0x1A		;- Area Size = 16KB
AREA_32KB		EQU	0x1C		;- Area Size = 32KB
AREA_64KB		EQU	0x1E		;- Area Size = 64KB
AREA_128KB		EQU	0x20		;- Area Size = 128KB
AREA_256KB		EQU	0x22		;- Area Size = 256KB
AREA_512KB		EQU	0x24		;- Area Size = 512KB
AREA_1MB		EQU	0x26		;- Area Size = 1MB
AREA_2MB		EQU	0x28		;- Area Size = 2MB
AREA_4MB		EQU	0x2A		;- Area Size = 4MB
AREA_8MB		EQU	0x2C		;- Area Size = 8MB
AREA_16MB		EQU	0x2E		;- Area Size = 16MB
AREA_32MB		EQU	0x30		;- Area Size = 32MB
AREA_64MB		EQU	0x32		;- Area Size = 64MB
AREA_128MB		EQU	0x34		;- Area Size = 128MB
AREA_256MB		EQU	0x36		;- Area Size = 256MB
AREA_512MB		EQU	0x38		;- Area Size = 512MB
AREA_1GB		EQU	0x3A		;- Area Size = 1GB
AREA_2GB		EQU	0x3C		;- Area Size = 2GB
AREA_4GB		EQU	0x3E		;- Area Size = 4GB

AREA_BASE_MASK		EQU	0xFFFFF000	;- Area Base Address Mask

;--------------------------------------------------------
;- Flush Command Register Definition (Register 7: c7)
;--------------------------------------------------------

CACHE_FLUSH		EQU	0xFFFFFFFF	;- A write of any data will flush all
						;- Cache unlocked banks

                END