cachec.h

ARM9200开发板的ROM boot程序源码1.0

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name           : cachec.h
//* Object              : Cache Header File.
//*
//* 1.0 25/01/01 ED     : Creation
//*----------------------------------------------------------------------------

#ifndef cachec_h
#define cachec_h

#define	BAD_ID_CODE				0xF			/* Bad Register Identifier */

/*-----------------------------------*/
/* CACHE_ID : Cache ID Register (c0) */
/*-----------------------------------*/

#define	CACHE_ID				0x0			/* Cache ID Register Identifier */

#define	CACHE_2KB				0xFF1C7400	/* 2KB Cache variant identifier */
#define	CACHE_4KB				0xFF2C7400	/* 4KB Cache variant identifier */
#define	CACHE_8KB				0xFF3C7400	/* 8KB Cache variant identifier */
#define	CACHE_16KB				0xFF4C7400	/* 16KB Cache variant identifier */

#define	CACHE_VERSION_MASK		0x0000000F	/* Cache Version Mask */

/*-----------------------------------*/
/* CACHE_CR : Control Register (c1)  */
/*-----------------------------------*/

#define	CACHE_CR				0x1			/* Cache CR Register Identifier */

#define	CACHE_DIS				0x0			/* Cache disabled */

#define	CACHE_PROTDIS_MASK		0xFFFFFFFE	/* On-chip protection unit disabled mask */
#define	CACHE_PROTEN			0x1			/* On-chip protection unit enabled */
#define	CACHE_DIS_MASK			0xFFFFFFFB	/* Cache disabled mask */
#define	CACHE_EN				0x4			/* Cache enabled */

#define	CACHE_SPLIT_MODE		0x1000000	/* Split Instruction/Data Mode control bit */
#define NO_SPLIT				0x0			/* No Instruction/Data Split */
#define	SPLIT_1INS_3DATA		0x2000000	/* 1 Bank Instruction, 3 Banks Data */
#define	SPLIT_2INS_2DATA		0x4000000	/* 2 Bank Instruction, 2 Banks Data */
#define	SPLIT_3INS_1DATA		0x6000000	/* 3 Bank Instruction, 1 Banks Data */

#define	CACHE_LOAD_MODE			0x8000000	/* Partially-locked Operation control bit */
#define	LOCK_0BANK				0x0			/* No Banks Locked */
#define	LOCK_1BANK				0x2000000	/* 1 Bank Locked */
#define	LOCK_2BANK				0x4000000	/* 2 Bank Locked */
#define	LOCK_3BANK				0x6000000	/* 3 Bank Locked */
#define	UNLOCK_ALL_MASK			0xF9FFFFFF	/* All Banks unlocked */

#define	CACHE_BANK0				0x0			/* Bank 0 */
#define	CACHE_BANK1				0x10000000	/* Bank 1 */
#define	CACHE_BANK2				0x20000000	/* Bank 2 */
#define	CACHE_BANK3				0x30000000	/* Bank 3 */
#define	CACHE_BANK0_MASK		0xCFFFFFFF	/* 0 Cache Banks Mask */

/*-------------------------------------*/
/* CACHE_CA : Cacheable Register (c2)  */
/*-------------------------------------*/

#define	CACHE_CA				0x2			/* Cache CA Register Identifier */

#define	CACHE_AREA_NB			0x8			/* Number of areas */

#define	CACHE_AREADIS			0x0			/* Area defined Uncacheable */

#define	CACHE_AREA0EN			0x1			/* Area 0 defined Cacheable */
#define	CACHE_AREA1EN			0x2			/* Area 1 defined Cacheable */
#define	CACHE_AREA2EN			0x4			/* Area 2 defined Cacheable */
#define	CACHE_AREA3EN			0x8			/* Area 3 defined Cacheable */
#define	CACHE_AREA4EN			0x10		/* Area 4 defined Cacheable */
#define	CACHE_AREA5EN			0x20		/* Area 5 defined Cacheable */
#define	CACHE_AREA6EN			0x40		/* Area 6 defined Cacheable */
#define	CACHE_AREA7EN			0x80		/* Area 8 defined Cacheable */

#define	CACHE_AREA0DIS_MASK		0xFFFFFFFE	/* Area 0 defined Uncacheable mask */
#define	CACHE_AREA1DIS_MASK		0xFFFFFFFD	/* Area 1 defined Uncacheable mask */
#define	CACHE_AREA2DIS_MASK		0xFFFFFFFB	/* Area 2 defined Uncacheable mask */
#define	CACHE_AREA3DIS_MASK		0xFFFFFFF7	/* Area 3 defined Uncacheable mask */
#define	CACHE_AREA4DIS_MASK		0xFFFFFFEF	/* Area 4 defined Uncacheable mask */
#define	CACHE_AREA5DIS_MASK		0xFFFFFFDF	/* Area 5 defined Uncacheable mask */
#define	CACHE_AREA6DIS_MASK		0xFFFFFFBF	/* Area 6 defined Uncacheable mask */
#define	CACHE_AREA7DIS_MASK		0xFFFFFF7F	/* Area 7 defined Uncacheable mask */

/*--------------------------------------*/
/* CACHE_PR : Protection Register (c5)  */
/*--------------------------------------*/

#define	CACHE_PR				0x5			/* Cache PR Register Identifier */

#define	CACHE_PROT_EN_MASK		0x3			/* Area Protection enable Mask */

#define	CACHE_AREA_NOACC		0x0			/* No Access to the Area in any Mode */
#define	CACHE_AREA_RWSUP		0x1			/* R/W Access in Supervisor Mode
											   No Access in User Mode */
#define	CACHE_AREA_RWSUP_ROUS	0x2			/* R/W Access in Supervisor Mode
											   Read-only Access in User Mode */
#define	CACHE_AREA_RWALL		0x3			/* R/W Access to the Area in any Mode */

#define	CACHE_AREA0MODE			0x0			/* Area 0 Protection Definition bits */
#define	CACHE_AREA1MODE			0x2			/* Area 1 Protection Definition bits */
#define	CACHE_AREA2MODE			0x4			/* Area 2 Protection Definition bits */
#define	CACHE_AREA3MODE			0x6			/* Area 3 Protection Definition bits */
#define	CACHE_AREA4MODE			0x8			/* Area 4 Protection Definition bits */
#define	CACHE_AREA5MODE			0xA			/* Area 5 Protection Definition bits */
#define	CACHE_AREA6MODE			0xC			/* Area 6 Protection Definition bits */
#define	CACHE_AREA7MODE			0xE			/* Area 7 Protection Definition bits */

/*--------------------------------------------------*/
/* CACHE_MR : Memory Area Definition Register (c6)  */
/*--------------------------------------------------*/

#define	CACHE_MR				0x6			/* Cache MR Register Identifier */

#define	AREA_DIS				0x0			/* Area disabled */

#define	AREA_DIS_MASK			0xFFFFFFFE	/* Area disable mask */
#define	AREA_EN					0x1			/* Area enabled */

#define	AREA_4KB				0x16		/* Area Size = 4KB */
#define	AREA_8KB				0x18		/* Area Size = 8KB */
#define	AREA_16KB				0x1A		/* Area Size = 16KB */
#define	AREA_32KB				0x1C		/* Area Size = 32KB */
#define	AREA_64KB				0x1E		/* Area Size = 64KB */
#define	AREA_128KB				0x20		/* Area Size = 128KB */
#define	AREA_256KB				0x22		/* Area Size = 256KB */
#define	AREA_512KB				0x24		/* Area Size = 512KB */
#define	AREA_1MB				0x26		/* Area Size = 1MB */
#define	AREA_2MB				0x28		/* Area Size = 2MB */
#define	AREA_4MB				0x2A		/* Area Size = 4MB */
#define	AREA_8MB				0x2C		/* Area Size = 8MB */
#define	AREA_16MB				0x2E		/* Area Size = 16MB */
#define	AREA_32MB				0x30		/* Area Size = 32MB */
#define	AREA_64MB				0x32		/* Area Size = 64MB */
#define	AREA_128MB				0x34		/* Area Size = 128MB */
#define	AREA_256MB				0x36		/* Area Size = 256MB */
#define	AREA_512MB				0x38		/* Area Size = 512MB */
#define	AREA_1GB				0x3A		/* Area Size = 1GB */
#define	AREA_2GB				0x3C		/* Area Size = 2GB */
#define	AREA_4GB				0x3E		/* Area Size = 4GB */

#define	AREA_BASE_MASK			0xFFFFF000	/* Area Base Address Mask */

/*--------------------------------------------------*/
/* CACHE_FC : Flush Command Register (c7)           */
/*--------------------------------------------------*/

#define	CACHE_FLUSH				0xFFFFFFFF	/* A write of any data will flush all
											   Cache unlocked banks */

#endif /* cachec_h */