lib_cachec.arm

ARM9200开发板的ROM boot程序源码1.0

;---------------------------------------------------------------------------------------------

	mov		r0, #CACHE_PROTEN	; setting the Protection Unit Enable bit
	orr		r0, r0, #CACHE_EN	; and oring with the Cache Enable bit
	mcr		p15, 0, r0, c1, c2, 0	; Writing the Control Register
	ldmia		sp!, {r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_bank_close
;- Object		: Disable the cache (c1)
;- Input Parameters	: None
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_bank_close
	
at91_cmbiu_bank_close
	stmdb		sp!, {r4-r12, r14}

;- Close the Cache by clearing the Protection Unit and Cache Enable bits in the Control Register
;-----------------------------------------------------------------------------------------------

	bl		at91_cmbiu_unlock_cmd	; Unlock and Flush all Banks
	mov		r0, #CACHE_DIS		; Clearing the Protection Unit Enable
						; and the Cache Enable bits
	mcr		p15, 0, r0, c1, c2, 0	; Writing the Control Register
	ldmia		sp!, {r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_flush_cmd
;- Object		: Flush all unlocked cache banks through
;-			: the Flush Command Register (c7)
;- Input Parameters	: None
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_flush_cmd
	
at91_cmbiu_flush_cmd
	stmdb		sp!, {r0, r4-r12, r14}

;- Flush all Unlocked Cache Banks by writing the Flush Command Register
;----------------------------------------------------------------------

	mvn		r0, #0			; CACHE_FLUSH
	mcr		p15, 0, r0, c7, c2, 0	; Causing a Flush of all Unlocked Cache Banks
	ldmia		sp!, {r0, r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_lock_cmd
;- Object		: Load the instructions or data indexed into the
;-			: selected Bank and lock it (c1)
;- Input Parameters	: r0 = bank to be locked number
;-			: r1 = base address of the data to be loaded
;-			: r2 = data to be loaded count
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_lock_cmd
	
at91_cmbiu_lock_cmd
	stmdb		sp!, {r4-r12, r14}
	mrc		p15, 0, r3, c1, c2, 0	; Reading the Control Register

;	and		r3, r3, #CACHE_BANK0_MASK;Resetting the Bank Field
	bic		r3, r3, 3 LSL #28
	
	orr		r3, r3, r0, LSL #3	; Oring with the Bank Number
	orr		r3, r3, #CACHE_LOAD_MODE; Oring with the F bit set to 1
	mcr		p15, 0, r3, c1, c2, 0	; Writing the Control Register
	bl		at91_cmbiu_flush_cmd	; Causing a Flush of all Unlocked Cache Banks
	add		r4, r1, r2		; Computing the last address of data to be loaded
load_loop
	cmp		r1, r4			; Load data
	bge		end_loop		; until last address
	ldmia		r1!, {r5-r8}		; not reached
	b		load_loop
end_loop
	mvn		r4, #CACHE_LOAD_MODE	; Anding with the one's
	and		r3, r3, r4		; complement of the F bit
	mcr		p15, 0, r3, c1, c2, 0	; Writing the Control Register
;	and		r3, r3, #UNLOCK_ALL_MASK; Resetting the Lock Field
	bic		r3, r3, 6 LSL #24
	orr		r3, r3, r0		; Oring with the Bank to be locked
	mcr		p15, 0, r3, c1, c2, 0	; Writing the Control Register
	ldmia		sp!, {r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_unlock_cmd
;- Object		: Unlock all cache banks through the Control Register (c1)
;- Input Parameters	: None
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_unlock_cmd
	
at91_cmbiu_unlock_cmd
	stmdb		sp!, {r0, r4-r12, r14}
	mrc		p15, 0, r0, c1, c2, 0	; Reading the Control Register
	
;	and		r0, r0, #UNLOCK_ALL_MASK; Anding with the Unlock All Banks Mask
	bic		r0, r0, 6 LSL #24
	
;	and		r0, r0, #CACHE_BANK0_MASK;Anding with the Cache Banks Mask
	bic		r0, r0, 3 LSL #28

	mcr		p15, 0, r0, c1, c2, 0	; Updating the Control Register
	bl		at91_cmbiu_flush_cmd	; Causing a Flush of all Unlocked Cache Banks
	ldmia		sp!, {r0, r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_split_cmd
;- Object		: Split Instruction/Data Mode Bank Allocation (c1)
;- Input Parameters	: r0 = bank allocation
;-			: r1 = base address of the code fragment to be loaded
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_split_cmd
	
at91_cmbiu_split_cmd
	stmdb		sp!, {r4-r12, r14}
	mrc		p15, 0, r2, c1, c2, 0	; Reading the Control Register
	orr		r2, r2, #CACHE_SPLIT_MODE	; Oring with the S bit set to 1
	
;	and		r2, r2, #CACHE_BANK0_MASK;Clearing the Cache Bank Field
	bic		r2, r2, 3 LSL #28

;	and		r2, r2, #UNLOCK_ALL_MASK; Clearing the Lock Field
	bic		r2, r2, 6 LSL #24
	
	orr		r2, r2, r0		; Oring with the new Split Allocation
	mcr		p15, 0, r2, c1, c2, 0	; Updating the Control Register
	cmp		r1, #0			; If a code fragment is to be loaded,
	beq		end_split
	bl		at91_cmbiu_flush_cmd	; Causes a Flush of all Unlocked Cache Banks,
	mov		lr, pc			; Saves the return address
	bx		r1			; And executes the required code fragment
end_split
	mvn		r3, #CACHE_SPLIT_MODE	; Anding with the one's
	and		r2, r2, r3		; complement of the S bit
	mcr		p15, 0, r2, c1, c2, 0	; Writing the Control Register
	ldmia		sp!, {r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_get_status
;- Object		: Get the required Register configuration
;- Input Parameters	: r0 = register identifier
;-			: r1 = area identifier
;- Output Parameters	: r0 = Register configuration
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_get_status
	
at91_cmbiu_get_status
	stmdb		sp!, {r4-r12, r14}
	
	cmp		r0, #CACHE_ID		; Detecting which Register
	beq		id_status		; is to be read
	cmp		r0, #CACHE_CR
	beq		cr_status
	cmp		r0, #CACHE_CA
	beq		ca_status
	cmp		r0, #CACHE_PR
	beq		pr_status
	cmp		r0, #CACHE_MR
	bne		bad_code
	mov		r4, #CACHE_AREA0EN
	mov		r4, r4, LSL r1
	cmp		r4, #CACHE_AREA0EN
	beq		mr0_status
	cmp		r4, #CACHE_AREA1EN
	beq		mr1_status
	cmp		r4, #CACHE_AREA2EN
	beq		mr2_status
	cmp		r4, #CACHE_AREA3EN
	beq		mr3_status
	cmp		r4, #CACHE_AREA4EN
	beq		mr4_status
	cmp		r4, #CACHE_AREA5EN
	beq		mr5_status
	cmp		r4, #CACHE_AREA6EN
	beq		mr6_status
	cmp		r4, #CACHE_AREA7EN
	beq		mr7_status
	
id_status
	mrc		p15, 0, r0, c0, c2, 0	; Reading the Cache ID Code
	b		end_get_status
	
cr_status
	mrc		p15, 0, r0, c1, c2, 0	; Reading the Control Register
	b		end_get_status
	
ca_status
	mrc		p15, 0, r0, c2, c2, 0	; Reading the Cacheable Register
	b		end_get_status
	
pr_status
	mrc		p15, 0, r0, c5, c2, 0	; Reading the Protection Register
	b		end_get_status
	
mr0_status
	mrc		p15, 0, r0, c6, c0, 0	; Reading the Memory Register Area 0
	b		end_get_status
	
mr1_status
	mrc		p15, 0, r0, c6, c1, 0	; Reading the Memory Register Area 1
	b		end_get_status
	
mr2_status
	mrc		p15, 0, r0, c6, c2, 0	; Reading the Memory Register Area 2
	b		end_get_status
	
mr3_status
	mrc		p15, 0, r0, c6, c3, 0	; Reading the Memory Register Area 3
	b		end_get_status
	
mr4_status
	mrc		p15, 0, r0, c6, c4, 0	; Reading the Memory Register Area 4
	b		end_get_status
	
mr5_status
	mrc		p15, 0, r0, c6, c5, 0	; Reading the Memory Register Area 5
	b		end_get_status
	
mr6_status
	mrc		p15, 0, r0, c6, c6, 0	; Reading the Memory Register Area 6
	b		end_get_status
	
mr7_status
	mrc		p15, 0, r0, c6, c7, 0	; Reading the Memory Register Area 7
	b		end_get_status
	
bad_code
	mov		r0, #BAD_ID_CODE	; Bad Command
	b		end_get_status
	
end_get_status
	ldmia		sp!, {r4-r12, r14}
	bx		lr

	END