lib_cachec.arm

ARM9200开发板的ROM boot程序源码1.0

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File source          : lib_cachec.arm
;- Object               : Assembler CMBIU Functions Library
;-
;- 1.0 22/01/01 ED      : Creation
;------------------------------------------------------------------------------

            AREA        CACHE, CODE, READONLY, INTERWORK

;-------------------------- List of Included Files ---------------------------

            INCLUDE     periph/cachec/cachec.inc


;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_area_open
;- Object		: Initialize a memory area (c2, c5, c6)
;- Input Parameters	: r0 = area number
;-			: r1 = area cacheable or not cacheable definition
;-			: r2 = area access protection definition
;-			: r3 = area base address and size definition
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_area_open
	
at91_cmbiu_area_open
	stmdb		sp!, {r4-r12, r14}
	
;- Setup the Area Cacheable definition
;-------------------------------------

	mrc		p15, 0, r4, c2, c2, 0	; Reading the Cacheable Register
	orr		r4, r4, r1		; Oring the Cacheable Register with
						; the new Area definition
	mcr		p15, 0, r4, c2, c2, 0	; Updating the Cacheable Register
	
;- Setup the Protection and Memory Area Registers
;------------------------------------------------

	orr		r3, r3, #AREA_EN	; Oring the Memory Area definition with
						; the Area Enable bit
	mrc		p15, 0, r4, c5, c2, 0	; Reading the Protection Register
area0_open
	mov		r5, #CACHE_AREA0MODE	; Detecting which Area is to be enabled
	cmp		r0, r5, LSR #1
	bne		area1_open
	orr		r4, r4, r2, LSL #CACHE_AREA0MODE; Oring the Protection Register with
							; the new Area Protection definition
	mcr		p15, 0, r4, c5, c2, 0	; Updating the Protection Register
	mcr		p15, 0, r3, c6, c0, 0	; Updating the Memory Area Register
	b		end_area_open
area1_open
	mov		r5, #CACHE_AREA1MODE
	cmp		r0, r5, LSR #1
	bne		area2_open
	orr		r4, r4, r2, LSL #CACHE_AREA1MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c1, 0
	b		end_area_open
area2_open
	mov		r5, #CACHE_AREA2MODE
	cmp		r0, r5, LSR #1
	bne		area3_open
	orr		r4, r4, r2, LSL #CACHE_AREA2MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c2, 0
	b		end_area_open
area3_open
	mov		r5, #CACHE_AREA3MODE
	cmp		r0, r5, LSR #1
	bne		area4_open
	orr		r4, r4, r2, LSL #CACHE_AREA3MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c3, 0
	b		end_area_open
area4_open
	mov		r5, #CACHE_AREA4MODE
	cmp		r0, r5, LSR #1
	bne		area5_open
	orr		r4, r4, r2, LSL #CACHE_AREA4MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c4, 0
	b		end_area_open
area5_open
	mov		r5, #CACHE_AREA5MODE
	cmp		r0, r5, LSR #1
	bne		area6_open
	orr		r4, r4, r2, LSL #CACHE_AREA5MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c5, 0
	b		end_area_open
area6_open
	mov		r5, #CACHE_AREA6MODE
	cmp		r0, r5, LSR #1
	bne		area7_open
	orr		r4, r4, r2, LSL #CACHE_AREA6MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c6, 0
	b		end_area_open
area7_open
	orr		r4, r4, r2, LSL #CACHE_AREA7MODE
	mcr		p15, 0, r4, c5, c2, 0
	mcr		p15, 0, r3, c6, c7, 0
end_area_open
	ldmia		sp!, {r4-r12, r14}
	bx		lr



;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_area_close
;- Object		: Disable a memory area (c2, c5, c6)
;- Input Parameters	: r0 = area number
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_area_close
	
at91_cmbiu_area_close
	stmdb		sp!, {r4-r12, r14}

;- Setup the Area Cacheable, Protection and Memory Registers
;-----------------------------------------------------------

	mov		r1, #AREA_DIS		; Erasing the Memory Area definitions
						; and disabling the Area
	mrc		p15, 0, r2, c2, c2, 0	; Reading the Cacheable Register
	mrc		p15, 0, r3, c5, c2, 0	; Reading the Protection Register
area0_close
	mov		r4, #CACHE_AREA0MODE	; Detecting which Area is to be disabled
	cmp		r0, r4, LSR #1
	bne		area1_close

	bic		r2, r2, #1			; Anding the Cacheable Register with	
	mcr		p15, 0, r2, c2, c2, 0	; Updating the Cacheable Register
	mov		r4, #CACHE_PROT_EN_MASK ; Storing the Protection Enable Mask
	mvn		r4, r4, LSL #CACHE_AREA0MODE ; Anding the Protection Register with
	and		r3, r3, r4		; the area no access definition
	mcr		p15, 0, r3, c5, c2, 0	; Updating the Protection Register
	mcr		p15, 0, r1, c6, c0, 0	; Updating the Memory Area Register
	b		end_area_close
area1_close
	mov		r4, #CACHE_AREA1MODE
	cmp		r0, r4, LSR #1
	bne		area2_close

	bic		r2, r2, #2
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA1MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c1, 0
	b		end_area_close
area2_close
	mov		r4, #CACHE_AREA2MODE
	cmp		r0, r4, LSR #1
	bne		area3_close

	bic		r2, r2, #4
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA2MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c2, 0
	b		end_area_close
area3_close
	mov		r4, #CACHE_AREA3MODE
	cmp		r0, r4, LSR #1
	bne		area4_close

	bic		r2, r2, #8
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA3MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c3, 0
	b		end_area_close
area4_close
	mov		r4, #CACHE_AREA4MODE
	cmp		r0, r4, LSR #1
	bne		area5_close
	
	bic		r2, r2, #0x10
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA4MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c4, 0
	b		end_area_close
area5_close
	mov		r4, #CACHE_AREA5MODE
	cmp		r0, r4, LSR #1
	bne		area6_close
	
	bic		r2, r2, #0x20
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA5MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c5, 0
	b		end_area_close
area6_close
	mov		r4, #CACHE_AREA6MODE
	cmp		r0, r4, LSR #1
	bne		area7_close
	
	bic		r2, r2, #0x40
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA6MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c6, 0
	b		end_area_close
area7_close

	bic		r2, r2, #0x80
	mcr		p15, 0, r2, c2, c2, 0
	mov		r4, #CACHE_PROT_EN_MASK
	mvn		r4, r4, LSL #CACHE_AREA7MODE
	and		r3, r3, r4
	mcr		p15, 0, r3, c5, c2, 0
	mcr		p15, 0, r1, c6, c7, 0
end_area_close
	ldmia		sp!, {r4-r12, r14}
	bx		lr

;------------------------------------------------------------------------------
;- Function Name	: at91_cmbiu_bank_open
;- Object		: Initialize the cache (c1)
;- Input Parameters	: None
;- Output Parameters	: None
;- Functions Called	: None
;------------------------------------------------------------------------------

	EXPORT		at91_cmbiu_bank_open
	
at91_cmbiu_bank_open
	stmdb		sp!, {r4-r12, r14}

;- Open the Cache by setting the Protection Unit and Cache Enable bits in the Control Register