📄 usart2.h
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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : usart2.h
//* Object : USART2 Header File.
//*
//* 1.0 25/09/01 HI : Creation
//*----------------------------------------------------------------------------
#ifndef usart2_h
#define usart2_h
#include "periph/stdc/std_c.h"
#include "periph/pio/lib_pio.h"
#include "periph/pdc2/pdc2.h"
/*-------------------------------------------*/
/* USART User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct _AT91S_USART2
{
at91_reg US_CR ; /* Control Register */
at91_reg US_MR ; /* Mode Register */
at91_reg US_IER ; /* Interrupt Enable Register */
at91_reg US_IDR ; /* Interrupt Disable Register */
at91_reg US_IMR ; /* Interrupt Mask Register */
at91_reg US_CSR ; /* Channel Status Register */
at91_reg US_RHR ; /* Receive Holding Register */
at91_reg US_THR ; /* Transmit Holding Register */
at91_reg US_BRGR ; /* Baud Rate Generator Register */
at91_reg US_RTOR ; /* Receiver Timeout Register */
at91_reg US_TTGR ; /* Transmitter Time-guard Register */
at91_reg Reserved0[5]; /* reserved */
at91_reg US_FIDI ; /* FI_DI Ratio Register */
at91_reg US_NER; /* ISO 7816 Nb errors register*/
at91_reg US_XXR; /* Xon Xoff Register */
at91_reg US_IF; /* IRDA Filter Register*/
at91_reg Reserved1[((0x100-0x4C)/4)-1] ;
AT91S_PDC2 usartPdc2; /* PDC channel registers for usart */
} AT91S_USART2, *AT91PS_USART2 ;
/*--------------------------*/
/* US_CR : Control Register */
/*--------------------------*/
#define US_RSTRX 0x0004 /* Reset Receiver */
#define US_RSTTX 0x0008 /* Reset Transmitter */
#define US_RXEN 0x0010 /* Receiver Enable */
#define US_RXDIS 0x0020 /* Receiver Disable */
#define US_TXEN 0x0040 /* Transmitter Enable */
#define US_TXDIS 0x0080 /* Transmitter Disable */
#define US_RSTSTA 0x0100 /* Reset Status Bits */
#define US_STTBRK 0x0200 /* Start Break */
#define US_STPBRK 0x0400 /* Stop Break */
#define US_STTTO 0x0800 /* Reset Time-out */
#define US_SENDA 0x1000 /* Send Address */
#define US_RSTIT 0x2000 /* Reset Iterations */
#define US_RSTNAK 0x4000 /* Reset Non Acknowledge (NACK)*/
#define US_RETT0 0x8000 /* Request To Rearm and start Time out*/
#define US_DTREN 0x10000 /* Data Terminal Ready Enable */
#define US_DTRDIS 0x20000 /* Data Terminal Ready Disable */
#define US_RTSEN 0x40000 /* Request To Send Enable */
#define US_RTSDIS 0x80000 /* Request To Send Disable */
/*-----------------------*/
/* US_MR : Mode Register */
/*-----------------------*/
#define US_MODE 0x07 /* USART Mode */
#define US_MODE_NORMAL 0x00 /* Normal Mode */
#define US_MODE_RS485 0x01 /* RS485 Mode */
#define US_MODE_HANDSHAKE 0x02 /* Handshaking Mode */
#define US_MODE_MODEM 0x03 /* Modem Mode */
#define US_MODE_7816_TXT0 0x04 /* ISO7816 Transmitter Protocol T=0 Mode */
#define US_MODE_7816_TXT1 0x06 /* ISO7816 Transmitter Protocol T=1 Mode */
#define US_MASK_MODE_7816 0x04
#define US_CLKS 0x0030 /* Clock Selection */
#define US_CLKS_MCK 0x00 /* Master Clock */
#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */
#define US_CLKS_SCK 0x20 /* External Clock */
#define US_CLKS_SLCK 0x30 /* Slow Clock */
#define US_CHRL 0x00C0 /* Byte Length */
#define US_CHRL_5 0x00 /* 5 bits */
#define US_CHRL_6 0x40 /* 6 bits */
#define US_CHRL_7 0x80 /* 7 bits */
#define US_CHRL_8 0xC0 /* 8 bits */
#define US_SYNC 0x0100 /* Synchronous Mode Enable */
#define US_PAR 0x0E00 /* Parity Mode */
#define US_PAR_EVEN 0x00 /* Even Parity */
#define US_PAR_ODD 0x200 /* Odd Parity */
#define US_PAR_SPACE 0x400 /* Space Parity to 0 */
#define US_PAR_MARK 0x600 /* Marked Parity to 1 */
#define US_PAR_NO 0x800 /* No Parity */
#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */
#define US_NBSTOP 0x3000 /* Stop Bit Number */
#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
#define US_CHMODE 0xC000 /* Channel Mode */
#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
#define US_ORDER_LSB 0x0 /* LSB First */
#define US_ORDER_MSB 0x10000 /* MSB First */
#define US_MODE9 0x20000 /* 9 Bit Mode */
#define US_CLKO 0x40000 /* Baud Rate Output Enable */
#define US_OVER_16 0x0 /* 16*Oversampling */
#define US_OVER_8 0x80000 /* 8*Oversampling */
#define US_REPRQ 0x100000 /* ISO7816 Protocol T=0 Receiver NACK generation */
#define US_MAX_ITERATION 0x7000000 /* ISO7816 Protocol T=0 Number of Repetitions Field */
#define US_MAX_ITERATION_SHIFT 24 /* Max iteration shift */
/* Mode Register model */
/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_SCK )
/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
#define US_SYNC_MODE ( US_SYNC + \
US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* SCK used Label */
#define SCK_USED (US_CLKO | US_CLKS_SCK)
/* Standard ISO T=0 Mode : 8 bits , 1 stop , parity */
#define US_ISO_READER_MODE ( US_MODE_7816_TXT0 + \
US_CLKS_MCK +\
US_NBSTOP_1 + \
US_PAR_EVEN + \
US_CHRL_8 + \
US_ORDER_LSB + \
US_CLKO +\
US_OVER_8)
/*---------------------------------------------------------------*/
/* US_IER, US_IDR, US_IMR, US_CSR: Status and Interrupt Register */
/*---------------------------------------------------------------*/
#define US_RXRDY 0x1 /* Receiver Ready */
#define US_TXRDY 0x2 /* Transmitter Ready */
#define US_RXBRK 0x4 /* Receiver Break */
#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */
#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */
#define US_OVRE 0x20 /* Overrun Error */
#define US_FRAME 0x40 /* Framing Error */
#define US_PARE 0x80 /* Parity Error */
#define US_TIMEOUT 0x100 /* Receiver Timeout */
#define US_TXEMPTY 0x200 /* Transmitter Empty */
#define US_ITERATION 0x400 /* ISO7816 Protocol T=0 Iteration */
#define US_TXBUFE 0x800 /* Buffer Empty */
#define US_RXBUFF 0x1000 /* Buffer Full */
#define US_NACK 0x2000 /* Non Acknowledge */
#define US_RIIC 0x10000 /* Ring Indicator Input */
#define US_DSRIC 0x20000 /* Data Set Ready Input */
#define US_DCDIC 0x40000 /* Data Carrier Detect Input */
#define US_CTSIC 0x80000 /* Clear To Send Input */
#define US_COMMRX 0x80000000 /* COMMRX = 1 */
#define US_COMMTX 0x40000000 /* COMMTX = 1 */
#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
/*-------------------------------------------------------*/
/* US_PTCR and US_PTSR: PDC Control and Status Registers */
/*-------------------------------------------------------*/
#define US_RXTEN 0x1 /* Receiver Transfer Enable */
#define US_TXTEN 0x100 /* Transmitter Transfer Enable*/
#define US_RXTDIS 0x2 /* Receiver Transfer Disable */
#define US_TXTDIS 0x200 /* Transmitter Transfer Disable */
#endif /* usart2_h */
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