sdramc.h

ARM9200开发板的ROM boot程序源码1.0

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : sdramc.h
//* Object              : SDRAM Controller Header File
//*
//* 1.0 26/01/01 ED     : Creation
//*----------------------------------------------------------------------------

#ifndef sdramc_h
#define sdramc_h

#include    "periph/stdc/std_c.h"

/*------------------------------------------------------*/
/* SDRAM Controller User Interface Structure Definition */
/*------------------------------------------------------*/

typedef struct _AT91S_SDRAMC
{
    at91_reg		SDRC_MR ;			/* Mode Register */
    at91_reg		SDRC_TR ;			/* Refresh Timer Register */
    at91_reg		SDRC_CR ;			/* Configuration Register */
    at91_reg		SDRC_SRR ;			/* Self Refresh Command Register */
    at91_reg		SDRC_LPR ;			/* Low Power Command Register */
    at91_reg		SDRC_IER ;			/* Interrupt Enable Register */
    at91_reg		SDRC_IDR ;			/* Interrupt Disable Register */
    at91_reg		SDRC_IMR ;			/* Interrupt Mask Register */
    at91_reg		SDRC_ISR ;			/* Interrupt Status Register */
}AT91S_SDRAMC, *AT91PS_SDRAMC ;

/*-------------------------*/
/* SDRC_MR : Mode Register */
/*-------------------------*/

#define	SDRC_MODE				0x0F		/* SDRAMC Access Mode or Command */
#define	SDRC_NORMAL_MODE		0x0			/* Normal Mode */
#define	SDRC_NOP_COMMAND		0x1			/* NOP Command issued while accessing */
#define	SDRC_PRECHARGE_CMD		0x2			/* All Banks Precharge Command issued while accessing */
#define	SDRC_LOAD_MR_CMD		0x3			/* Load Mode Register Command issued while accessing */
#define	SDRC_REFRESH_CMD		0x4			/* Refresh Command issued while accessing */

#define	SDRC_DBW_MASK			0x10		/* SDRAMC data bus width mode */
#define	SDRC_16BIT_MODE			0x10		/* 16 bit data bus width */
#define	SDRC_32BIT_MODE			0x0			/* 32 bit data bus width */

/*----------------------------------*/
/* SDRC_TR : Refresh Timer Register */
/*----------------------------------*/

#define	SDRC_TIMER_COUNT_MASK	0x0FFF		/* SDRAMC Timer Count Field */

/*----------------------------------*/
/* SDRC_CR : Configuration Register */
/*----------------------------------*/

#define	SDRC_NC_MASK			0x3			/* Number of column bits selection */
#define	SDRC_8_COL_BIT			0x0			/* 8 bits */
#define	SDRC_9_COL_BIT			0x1			/* 9 bits */
#define	SDRC_10_COL_BIT			0x2			/* 10 bits */
#define	SDRC_11_COL_BIT			0x3			/* 11 bits */

#define	SDRC_NR_MASK			0xC			/* Number of row bits selection */
#define	SDRC_11_ROW_BIT			0x0			/* 11 bits */
#define	SDRC_12_ROW_BIT			0x4			/* 12 bits */
#define	SDRC_13_ROW_BIT			0x8			/* 13 bits */

#define	SDRC_NB_MASK			0x10		/* Number of banks selection */
#define	SDRC_2_BANK_BIT			0x0			/* 2 banks */
#define	SDRC_4_BANK_BIT			0x10		/* 4 bits */

#define	SDRC_CAS_MASK			0x60		/* Number of CAS latency cycles */
#define	SDRC_1_LAT_CYCLE		0x20		/* 1 latency cycle */
#define	SDRC_2_LAT_CYCLE		0x40		/* 2 latency cycle */
#define	SDRC_3_LAT_CYCLE		0x60		/* 3 latency cycle */

#define	SDRC_TWR_MASK			0x780		/* Number of Write Recovery Time cycles */
#define	SDRC_TWR_SHIFT			0x7			/* Logical Left Shift to be applied for Twr */
#define	SDRC_TWR_DEF			0x100		/* Default number = 2 clock cycles */

#define	SDRC_TRC_MASK			0x7800		/* Number of clock cycles between a Refresh
											   and an Active Command */
#define	SDRC_TRC_SHIFT			0xB			/* Logical Left Shift to be applied for Trc */
#define	SDRC_TRC_DEF			0x4000		/* Default number = 8 clock cycles */

#define	SDRC_TRP_MASK			0x78000		/* Number of clock cycles between a Precharge Command
											   and another Command */
#define	SDRC_TRP_SHIFT			0xF			/* Logical Left Shift to be applied for Trp */
#define	SDRC_TRP_DEF			0x18000		/* Default number = 3 clock cycles */

#define	SDRC_TRCD_MASK			0x780000	/* Number of clock cycles between an Active Command
											   and a Read/Write Command */
#define	SDRC_TRCD_SHIFT			0x13		/* Logical Left Shift to be applied for Trcd */
#define	SDRC_TRCD_DEF			0xC0000		/* Default number = 3 clock cycles */

#define	SDRC_TRAS_MASK			0x7800000	/* Number of clock cycles between an Active Command
											   and a Precharge Command */
#define	SDRC_TRAS_SHIFT			0x17		/* Logical Left Shift to be applied for Tras */
#define	SDRC_TRAS_DEF			0x2800000	/* Default number = 5 clock cycles */

#define	SDRC_TXSR_MASK			0x78000000	/* Number of clock cycles between CKE high
											   and an Active Command */
#define	SDRC_TXSR_SHIFT			0x1B		/* Logical Left Shift to be applied for Txsr */
#define	SDRC_TXSR_DEF			0x28000000	/* Default number = 5 clock cycles */

/*------------------------------------------*/
/* SDRC_SRR : Self Refresh Command Register */
/*------------------------------------------*/

#define	SDRC_SRM				0x1			/* SDRAMC Self Refresh mode */
#define	SDRC_SRCB_MASK			0x1			/* SDRAMC Self Refresh Field Mask */
#define	SDRC_SR_MODE			0x1			/* Self Refresh Command Bit */

/*---------------------------------------*/
/* SDRC_LPR : Low Power Command Register */
/*---------------------------------------*/

#define	SDRC_LPM				0x2			/* SDRAMC Low Power mode activated */
#define	SDRC_NO_LPM				0x3			/* SDRAMC Low Power mode deactivated */
#define	SDRC_LPCB_MASK			0x1			/* SDRAMC Low Power Field Mask */
#define	SDRC_LP_MODE			0x1			/* Low Power Activation Command Bit */
#define	SDRC_NO_LP_MODE			0x0			/* Low Power Deactivation Command Bit */

/*------------------------------------------------------------------------*/
/* SDRC_IER, SDRC_IDR, SDRC_IMR, SDRC_ISR: Status and Interrupt Registers */
/*------------------------------------------------------------------------*/

#define SDRC_RES				0x1         /* Refresh Error Status */

/*--------------------------------*/
/* SDRAM Mode Register Definition */
/*--------------------------------*/

#define	SDRAM_BL_1				0x0			/* SDRAM accesses burst length = 1 */
#define	SDRAM_BL_2				0x1			/* SDRAM accesses burst length = 2 */
#define	SDRAM_BL_4				0x2			/* SDRAM accesses burst length = 4 */

#define SDRAM_SEQ_BT			0x0			/* SDRAM sequential burst type accesses */
#define SDRAM_INT_BT			0x8			/* SDRAM interleaved burst type accesses */

#define	SDRAM_CAS_LAT_2			0x20		/* 2 CAS latency cycles */
#define	SDRAM_CAS_LAT_3			0x30		/* 3 CAS latency cycles */

#endif /* sdramc_h */