lib_sdramc.c

ARM9200开发板的ROM boot程序源码1.0

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : lib_sdramc.c
//* Object              : SDRAMC functions Library.
//*
//* 1.0 01/02/01 ED     : Creation
//*----------------------------------------------------------------------------

#include <stddef.h>
#include "periph/sdramc/lib_sdramc.h"

//*----------------------------------------------------------------------------
//* Function Name       : at91_sdramc_open
//* Object              : Initialize a SDRAM Controller.
//* Input Parameters    : <sdramc_desc>  = SDRAM Controller Descriptor
//*                     : <sdram_desc>   = SDRAM Device Parameters Descriptor
//*						: <base_address> = SDRAM Device base address
//*                     : <wait_desc>    = WAIT Descriptor
//* Output Parameters   : None
//* Functions called    : at91_wait_open
//*----------------------------------------------------------------------------
void at91_sdramc_open ( const SdramcDesc *sdramc_desc, ParamSdramDesc *sdram_desc,
						u_int *base_address, WaitDesc *wait_desc )
//* Begin
{
	u_int	i, j ;
	u_int	mode_reg_mirror ;
	u_int	mode_register ;
	u_int	latency_mode ;

	/* Program Memory Controller Interface */

    //* Program first temporizing period
    wait_desc->period = ( u_int ) WAIT_100US ;
    at91_wait_open ( wait_desc ) ;

	//* Data-path width programmation
	sdramc_desc->sdramc_base->SDRC_MR = sdram_desc->data_bus_width ;

	//* Configuration Register programmation
	if ( sdram_desc->twr == 0 )
		sdram_desc->twr = ( u_int ) SDRC_TWR_DEF ;
	else
		sdram_desc->twr = ( ( ( sdram_desc->twr * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TWR_SHIFT ;

	if ( sdram_desc->trc == 0 )
		sdram_desc->trc = ( u_int ) SDRC_TRC_DEF ;
	else
		sdram_desc->trc = ( ( ( sdram_desc->trc * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TRC_SHIFT ;

	if ( sdram_desc->trp == 0 )
		sdram_desc->trp = ( u_int ) SDRC_TRP_DEF ;
	else
		sdram_desc->trp = ( ( ( sdram_desc->trp * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TRP_SHIFT ;

	if ( sdram_desc->trcd == 0 )
		sdram_desc->trcd = ( u_int ) SDRC_TRCD_DEF ;
	else
		sdram_desc->trcd = ( ( ( sdram_desc->trcd * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TRCD_SHIFT ;

	if ( sdram_desc->tras == 0 )
		sdram_desc->tras = ( u_int ) SDRC_TRAS_DEF ;
	else
		sdram_desc->tras = ( ( ( sdram_desc->tras * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TRAS_SHIFT ;

	if ( sdram_desc->txsr == 0 )
		sdram_desc->txsr = ( u_int ) SDRC_TXSR_DEF ;
	else
		sdram_desc->txsr = ( ( ( sdram_desc->txsr * wait_desc->mcki_khz ) / 1000000 ) + 1 )
								<< SDRC_TXSR_SHIFT ;

	//* CAS Latency to be stucked at 2 for this SDRAM Controller revision
	sdram_desc->cas_latency = SDRC_2_LAT_CYCLE ;

	sdramc_desc->sdramc_base->SDRC_CR = ( sdram_desc->col_nb | sdram_desc->row_nb
										| sdram_desc->bank_nb | sdram_desc->cas_latency
										| sdram_desc->twr | sdram_desc->trc
										| sdram_desc->trp | sdram_desc->trcd
										| sdram_desc->tras | sdram_desc->txsr ) ;

	//* SDRAM Mode Register programmation
	latency_mode = ( sdram_desc->cas_latency ) >> 1 ;
	//* CAS Latency to be stucked at 2 for this SDRAM Controller revision
	latency_mode = ( u_int ) SDRAM_CAS_LAT_2 ;
	mode_register = ( sdram_desc->burst_length | sdram_desc->burst_type | latency_mode ) ;

    //* Program second temporizing period
    wait_desc->period = ( u_int ) WAIT_1MS ;
    at91_wait_open ( wait_desc ) ;

	//* Nop command
	mode_reg_mirror = sdramc_desc->sdramc_base->SDRC_MR & ~ ( u_int ) SDRC_MODE ;
	mode_reg_mirror |= ( u_int ) SDRC_NOP_COMMAND ;
	sdramc_desc->sdramc_base->SDRC_MR = mode_reg_mirror ;
	j = *base_address ;

    //* Program third temporizing period
    wait_desc->period = ( u_int ) WAIT_200US ;
    at91_wait_open ( wait_desc ) ;

    //* Precharge All command
	mode_reg_mirror = sdramc_desc->sdramc_base->SDRC_MR & ~ ( u_int ) SDRC_MODE ;
	mode_reg_mirror |= ( u_int ) SDRC_PRECHARGE_CMD ;
	sdramc_desc->sdramc_base->SDRC_MR = mode_reg_mirror ;
	j = *base_address ;

	//* Perform 8 Refresh command
	mode_reg_mirror = sdramc_desc->sdramc_base->SDRC_MR & ~ ( u_int ) SDRC_MODE ;
	mode_reg_mirror |= ( u_int ) SDRC_REFRESH_CMD ;
	sdramc_desc->sdramc_base->SDRC_MR = mode_reg_mirror ;
	for ( i=0 ; i <8 ; i++ )
		j = *base_address ;

	//* Load Mode Register command
	mode_reg_mirror = sdramc_desc->sdramc_base->SDRC_MR & ~ ( u_int ) SDRC_MODE ;
	mode_reg_mirror |= ( u_int ) SDRC_LOAD_MR_CMD ;
	sdramc_desc->sdramc_base->SDRC_MR = mode_reg_mirror ;
	j = *( u_int * ) ( ( u_int ) base_address + mode_register ) ;

	//* Normal Mode command
	mode_reg_mirror = sdramc_desc->sdramc_base->SDRC_MR & ~ ( u_int ) SDRC_MODE ;
	mode_reg_mirror |= ( u_int ) SDRC_NORMAL_MODE ;
	sdramc_desc->sdramc_base->SDRC_MR = mode_reg_mirror ;
	j = *base_address ;

	//* Refresh Timer Register programmation
	sdram_desc->tref = ( ( sdram_desc->tref * wait_desc->mcki_khz ) / 1000 ) ;
	sdramc_desc->sdramc_base->SDRC_TR = ( sdram_desc->tref & ( u_int ) SDRC_TIMER_COUNT_MASK ) ;

//* End
}

//*----------------------------------------------------------------------------
//* Function Name       : at91_sdramc_close
//* Object              : Disable a SDRAM Controller.
//* Input Parameters    : <sdramc_desc>  = SDRAM Controller Descriptor
//* Output Parameters   : None
//* Functions called    : None
//*----------------------------------------------------------------------------
void at91_sdramc_close ( const SdramcDesc *sdramc_desc )
//* Begin
{
	/* Program Memory Controller Interface */

    //* Disable all interrupts
    sdramc_desc->sdramc_base->SDRC_IDR = ( u_int ) SDRC_RES ;

//* End
}

//*----------------------------------------------------------------------------
//* Function Name       : at91_sdramc_trig_cmd
//* Object              : Perform a command to the SDRAM Controller.
//* Input Parameters    : <sdramc_desc> = SDRAM Descriptor
//*                     : <cmd>      	= Command Description
//* Output Parameters   : none
//* Functions called    : none
//*----------------------------------------------------------------------------
void at91_sdramc_trig_cmd ( const SdramcDesc *sdramc_desc, u_int cmd )
//* Begin
{

    switch ( cmd )
    {
		case ( u_int ) SDRC_SRM :

    		//* Write the command in the Self Refresh Command Register
			sdramc_desc->sdramc_base->SDRC_SRR = ( u_int ) SDRC_SR_MODE ;

			break ;

		case ( u_int ) SDRC_LPM :

    		//* Write the command in the Low Power Command Register
			sdramc_desc->sdramc_base->SDRC_LPR = ( u_int ) SDRC_LP_MODE ;

			break ;

		case ( u_int ) SDRC_NO_LPM :

    		//* Write the command in the Low Power Command Register
			sdramc_desc->sdramc_base->SDRC_LPR = ( u_int ) SDRC_NO_LP_MODE ;

			break ;

		default :

			break ;
	}

//* End
}

//*-----------------------------------------------------------------------------
//* Function Name       : at91_sdramc_get_status
//* Object              : Return the Configuration Register Programmation
//* Input Parameters    : <sdramc_desc>  = SDRAM Descriptor
//* Output Parameters   : <cfg>          = Configuration Register value
//* Functions called    : None
//*-----------------------------------------------------------------------------
u_int at91_sdramc_get_status ( const SdramcDesc *sdramc_desc )
//* Begin
{
    u_int cfg = sdramc_desc->sdramc_base->SDRC_CR ;

    return ( cfg ) ;

//* End
}