sdramc.inc

ARM9200开发板的ROM boot程序源码1.0

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File Name            : sdramc.inc
;- Object               : Assembler SDRAM Controller Definition File.
;-
;- 1.0 30/01/01 ED      : Creation
;------------------------------------------------------------------------------

;------------------------------------------------------
; SDRAM Controller User Interface Structure Definition
;------------------------------------------------------

                ^       0
SDRC_MR		#	4	;- Mode Register
SDRC_TR		#	4	;- Refresh Timer Register
SDRC_CR		#	4	;- Configuration Register
SDRC_SRR	#	4	;- Self Refresh Command Register
SDRC_LPR	#	4	;- Low Power Command Register
SDRC_IER	#	4	;- Interrupt Enable Register
SDRC_IDR	#	4	;- Interrupt Disable Register
SDRC_IMR	#	4	;- Interrupt Mask Register
SDRC_ISR	#	4	;- Interrupt Status Register

;--------------------------
;- SDRC_MR : Mode Register
;--------------------------

SDRC_MODE		EQU	0x0F		;- SDRAMC Access Mode or Command
SDRC_NORMAL_MODE	EQU	0x0		;- Normal Mode
SDRC_NOP_COMMAND	EQU	0x1		;- NOP Command issued while accessing
SDRC_PRECHARGE_CMD	EQU	0x2		;- All Banks Precharge Command issued while accessing
SDRC_LOAD_MR_CMD	EQU	0x3		;- Load Mode Register Command issued while accessing
SDRC_REFRESH_CMD	EQU	0x4		;- Refresh Command issued while accessing

SDRC_DBW_MASK		EQU	0x10		;- SDRAMC data bus width mode
SDRC_16BIT_MODE		EQU	0x10		;- 16 bit data bus width
SDRC_32BIT_MODE		EQU	0x0		;- 32 bit data bus width

;-----------------------------------
;- SDRC_TR : Refresh Timer Register
;-----------------------------------

SDRC_TIMER_COUNT_MASK	EQU	0x0FFF		;- SDRAMC Timer Count Field

;-----------------------------------
;- SDRC_CR : Configuration Register
;-----------------------------------

SDRC_NC_MASK		EQU	0x3		;- Number of column bits selection
SDRC_8_COL_BIT		EQU	0x0		;- 8 bits
SDRC_9_COL_BIT		EQU	0x1		;- 9 bits
SDRC_10_COL_BIT		EQU	0x2		;- 10 bits
SDRC_11_COL_BIT		EQU	0x3		;- 11 bits

SDRC_NR_MASK		EQU	0xC		;- Number of row bits selection
SDRC_11_ROW_BIT		EQU	0x0		;- 11 bits
SDRC_12_ROW_BIT		EQU	0x4		;- 12 bits
SDRC_13_ROW_BIT		EQU	0x8		;- 13 bits

SDRC_NB_MASK		EQU	0x10		;- Number of banks selection
SDRC_2_BANK_BIT		EQU	0x0		;- 2 banks
SDRC_4_BANK_BIT		EQU	0x10		;- 4 bits

SDRC_CAS_MASK		EQU	0x60		;- Number of CAS latency cycles
SDRC_1_LAT_CYCLE	EQU	0x20		;- 1 latency cycle
SDRC_2_LAT_CYCLE	EQU	0x40		;- 2 latency cycle
SDRC_3_LAT_CYCLE	EQU	0x60		;- 3 latency cycle

SDRC_TWR_MASK		EQU	0x780		;- Number of Write Recovery Time cycles
SDRC_TWR_DEF		EQU	0x100		;- Default number = 2 clock cycles

SDRC_TRC_MASK		EQU	0x7800		;- Number of clock cycles between a Refresh
						;- and an Active Command
SDRC_TRC_DEF		EQU	0x4000		;- Default number = 8 clock cycles

SDRC_TRP_MASK		EQU	0x78000		;- Number of clock cycles between a Precharge Command
						;- and another Command
SDRC_TRP_DEF		EQU	0x18000		;- Default number = 3 clock cycles

SDRC_TRCD_MASK		EQU	0x780000	;- Number of clock cycles between an Active Command
						;- and a Read/Write Command
SDRC_TRCD_DEF		EQU	0xC0000		;- Default number = 3 clock cycles

SDRC_TRAS_MASK		EQU	0x7800000	;- Number of clock cycles between an Active Command
						;- and a Precharge Command
SDRC_TRAS_DEF		EQU	0x2800000	;- Default number = 5 clock cycles

SDRC_TXSR_MASK		EQU	0x78000000	;- Number of clock cycles between CKE high
						;- and an Active Command
SDRC_TXSR_DEF		EQU	0x28000000	;- Default number = 5 clock cycles

;----------------------------------------
;- SDRC_SRR : Self Refresh Command Register
;----------------------------------------

SDRC_SRM		EQU	0x1		;- SDRAMC Self Refresh mode
SDRC_SRCB_MASK		EQU	0x1		;- SDRAMC Self Refresh Field Mask
SDRC_SR_MODE		EQU	0x1		;- Self Refresh Command Bit

;----------------------------------------
;- SDRC_LPR : Low Power Command Register
;----------------------------------------

SDRC_LPM		EQU	0x2		;- SDRAMC Low Power mode activated
SDRC_NO_LPM		EQU	0x3		;- SDRAMC Low Power mode deactivated
SDRC_LPCB_MASK		EQU	0x1		;- SDRAMC Low Power Field Mask
SDRC_LPR_MODE		EQU	0x1		;- Low Power Activation Command Bit
SDRC_NO_LPR_MODE	EQU	0x0		;- Low Power Deactivation Command Bit

;-------------------------------------------------------------------------
;- SDRC_IER, SDRC_IDR, SDRC_IMR, SDRC_ISR: Status and Interrupt Registers
;-------------------------------------------------------------------------

SDRC_RES		EQU	0x1         	;- Refresh Error Status

;---------------------------------
;- SDRAM Mode Register Definition
;---------------------------------

SDRAM_BL_1		EQU	0x0		;- SDRAM accesses burst length = 1
SDRAM_BL_2		EQU	0x1		;- SDRAM accesses burst length = 2
SDRAM_BL_4		EQU	0x2		;- SDRAM accesses burst length = 4

SDRAM_SEQ_BT		EQU	0x0		;- SDRAM sequential burst type accesses
SDRAM_INT_BT		EQU	0x8		;- SDRAM interleaved burst type accesses

SDRAM_CAS_LAT_2		EQU	0x20		;- 2 CAS latency cycles
SDRAM_CAS_LAT_3		EQU	0x30		;- 3 CAS latency cycles


                END