old_spi.h

ARM9200开发板的ROM boot程序源码1.0

//*---------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name           : spi.h
//* Object              : Serial Peripheral Interface Definition File
//*
//* 1.0 01/04/00 JCZ    : Creation
//*---------------------------------------------------------------------------

#ifndef spi_h
#define spi_h

/*--------------------------*/
/* SPI Structure Definition */
/*--------------------------*/

typedef struct _AT91S_SPI
{
    at91_reg        SP_CR ;			/* Control Register 		0x00 */
    at91_reg        SP_MR ;			/* Mode Register 			0x04 */
    at91_reg        SP_RDR ;		/* Receive Data Register	0x08 */
    at91_reg        SP_TDR ;		/* Transmit Data Register 	0x10 */
    at91_reg        SP_SR ;			/* Status Register 			0x14 */
    at91_reg        SP_IER ;		/* Interrupt Enable Reg		0x18 */
    at91_reg        SP_IDR ;		/* Interrupt Disable Reg	0x1C */
    at91_reg        SP_IMR ;		/* Interrupt Mask Register 	0x20 */
    at91_reg        reserved0[4]; 	/* Receive Pointer_Reg	0x24..0x2C */
    at91_reg        SP_CSR[4];		/* Chip Select Reg 0 to 3 	0x30..0x3C */

    at91_reg		reserved[((0x100 - 0x3C)/4)-1];

    at91_reg        SP_RPR ;		/* Receiver Pointer Register */
	at91_reg        SP_RCR ;		/* Receiver Counter Register */
	at91_reg        SP_TPR ;		/* Transmitter Pointer Register */
	at91_reg        SP_TCR ;		/* Transmitter Counter Register */
	at91_reg        SP_RNPR ;		/* Receiver Next Pointer Register */
	at91_reg        SP_RNCR ;		/* Receiver Next Counter Register */
	at91_reg        SP_TNPR ;		/* Transmitter Next Pointer Register */
	at91_reg        SP_TNCR ;		/* Transmitter Next Counter Register */
	at91_reg        SP_PTCR ;		/* PDC Transfer Control Register */
	at91_reg        SP_PTSR ;		/* PDC Transfer Status Register */
} AT91S_SPI, *AT91PS_SPI ;

/*------------------*/
/* Control Register */
/*------------------*/

#define SP_SPIEN                0x1         /* SPI Enable */
#define SP_SPIDIS               0x2         /* SPI Disable */
#define SP_SWRST                0x80        /* SPI Software Reset */

/*---------------*/
/* Mode Register */
/*---------------*/

#define SP_MSTR                 0x01         /* Master Mode Select */

#define SP_PS                   0x02         /* Peripheral Select */
#define SP_PS_FIXED             0x00         /* Fixed Peripheral Select */
#define SP_PS_VARIABLE          0x02         /* Variable Peripheral Select */

#define SP_PCSDEC               0x04         /* Chip Select Decode */
#define SP_DIV32                0x08         /* Clock Selection */
#define SP_MODEFAULT_DIS		0x10
#define SP_LLB                  0x80        /* Local Loopback */

#define SP_PCS                  0xF0000     /* Peripheral Chip Select */
#define SP_PCS0                 0xE0000     /* Chip Select 0 */
#define SP_PCS1                 0xD0000     /* Chip Select 1 */
#define SP_PCS2                 0xB0000     /* Chip Select 2 */
#define SP_PCS3                 0x70000     /* Chip Select 3 */

#define SP_DLYBCS               0xFF000000  /* Delay Before Chip Selects */

/*-----------------*/
/* Status Register */
/*-----------------*/

#define SP_RDRF                 0x1         /* Receive Data Register Full */
#define SP_TDRE                 0x2         /* Transmitte Data Register Empty */
#define SP_MODF                 0x4         /* Mode Fault */
#define SP_OVRES                0x8         /* Overrun Error Status */
#define SP_ENDRX                0x10        /* End of Receiver Transfer */
#define SP_ENDTX                0x20        /* End of Transmitter Transfer */
#define SP_SPIENS               0x10000     /* SPI Enable Status */

/*------------------------------------*/
/* Receive and Transmit Data Register */
/*------------------------------------*/

#define SP_RD                   0xFFFF      /* Receive Data */
#define SP_TD                   0xFFFF      /* Transmit Data */

/*----------------------*/
/* Chip Select Register */
/*----------------------*/

#define SP_CPOL                 0x1         /* Clock Polarity */
#define SP_NCPHA                0x2         /* Clock Phase */
#define SP_BITS                 0xF0        /* Bits Per Transfer */

#define SP_BITS                 0xF0        /* Bits Per Transfer */
#define SP_BITS_8               0x00        /* 8 Bits Per Transfer */
#define SP_BITS_9               0x10        /* 9 Bits Per Transfer */
#define SP_BITS_10              0x20        /* 10 Bits Per Transfer */
#define SP_BITS_11              0x30        /* 11 Bits Per Transfer */
#define SP_BITS_12              0x40        /* 12 Bits Per Transfer */
#define SP_BITS_13              0x50        /* 13 Bits Per Transfer */
#define SP_BITS_14              0x60        /* 14 Bits Per Transfer */
#define SP_BITS_15              0x70        /* 15 Bits Per Transfer */
#define SP_BITS_16              0x80        /* 16 Bits Per Transfer */

#define SP_SCBR                 0xFF00      /* Serial Clock Baud Rate */
#define SP_DLYBS                0xFF0000    /* Delay Before SPCK */
#define SP_DLYBCT               0xFF000000  /* Delay Between Consecutive Transfer */

#define SP_TXTEN				0x100
#define SP_RXTEN				0x01
#define SP_TXTDIS				0x200
#define SP_RXTDIS				0x2

#endif /* spi_h */