lib_udp.paf.arm

来自「ARM9200开发板的ROM boot程序源码1.0」· ARM 代码 · 共 2,376 行 · 第 1/2 页

ARM
2,376 行
字号
12
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#define APMC_CPU_EN		0x1		
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#define APMC_USB_EN		0x2		
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#define APMC_PCK0		0x100		
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#define APMC_PCK1		0x100		
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#define APMC_PCK2		0x100		
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#define APMC_PCK3		0x100		
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#define APMC_PCK4		0x100		
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#define APMC_PCK5		0x100		
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#define APMC_PCK6		0x100		
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#define APMC_PCK7		0x100		
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#define APMC_SSC0		0x4		
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#define APMC_SSC1		0x8		
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#define APMC_SSC2		0x10		
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#define APMC_US0		0x20		
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#define APMC_US1		0x40		
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#define APMC_US2		0x80		
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#define APMC_US3		0x100		
#line 19
#define APMC_SPI0		0x200		
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#define APMC_SPI1		0x400		
#line 19
#define APMC_TC0		0x800		
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#define APMC_TC1		0x1000		
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#define APMC_TC2		0x2000		
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#define APMC_TC3		0x4000		
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#define APMC_TC4		0x8000		
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#define APMC_TC5		0x10000		
#line 19
#define APMC_PIO0		0x20000		
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#define APMC_PIO1		0x40000		
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#define APMC_DAC		0x80000		
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#define APMC_ADC0		0x100000	
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#define APMC_ADC1		0x200000	
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#define APMC_ADC2		0x400000	
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#define APMC_ADC3		0x800000	
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#define APMC_USB		0x1000000	
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#define APMC_MOSCEN		0x1		
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#define APMC_DIVIDER_NONE			0x0	
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#define APMC_DIVIDER_INPUT			0x1	
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#define APMC_CLK_RANGE_40_TO_250MHZ 		0x0000	
#line 19
#define APMC_CLK_RANGE_20_TO_40MHZ  		0x4000 	
#line 19
#define APMC_CLK_RANGE_10_TO_20MHZ  		0x8000	
#line 19
#define APMC_CLK_RANGE_5_TO_10MHZ   		0xC000	
#line 19

#line 19
#define APCM_USB_PLL				0x20000000 	
#line 19
#define APMC_PLL_TEST				0x40000000 	
#line 19
#define APMC_PLL_EN				0x80000000 	
#line 19

#line 19
#define APMC_PLL_MULT_FACTOR_SHIFT		16
#line 19
#define APMC_CLK_RANGE_OUT_SHIFT		14
#line 19
#define APMC_PLL_STARTUP_MAX_SHIFT		8
#line 19
 
#line 19

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#line 19
#define APMC_MCK				0x0
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#define APMC_MCKS_32K				0x0	
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#define APMC_MCKS_MAIN				0x1	
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#define APMC_MCKS_PLLA				0x2	
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#define APMC_MCKS_PLLB				0x3	
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#line 19
#define APMC_DIVMCK_NONE			0x0	
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#define APMC_DIVMCK_DIV2			0x04	
#line 19
#define APMC_DIVMCK_DIV4			0x08	
#line 19
#define APMC_DIVMCK_DIV8			0x0C	
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#define APMC_DIVMCK_DIV16			0x10	
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#define APMC_DIVMCK_DIV32			0x14	
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#define APMC_DIVMCK_DIV64			0x18	
#line 19

#line 19
#define APMC_DIVMCK_SHIFT			2
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#line 19

#line 19
#define APMC_PCKS_32K				0x0	
#line 19
#define APMC_PCKS_MAIN				0x1	
#line 19
#define APMC_PCKS_PLLA				0x2	
#line 19
#define APMC_PCKS_PLLB				0x3	
#line 19

#line 19
#define APMC_DIVPCK_NONE			0x0	
#line 19
#define APMC_DIVPCK_DIV2			0x04	
#line 19
#define APMC_DIVPCK_DIV4			0x08	
#line 19
#define APMC_DIVPCK_DIV8			0x0C	
#line 19
#define APMC_DIVPCK_DIV16			0x10	
#line 19
#define APMC_DIVPCK_DIV32			0x14	
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#define APMC_DIVPCK_DIV64			0x18	
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#define APMC_MAIN_RDY				0x1	
#line 19
#define APMC_PLLA_RDY				0x2	
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#define APMC_PLLB_RDY				0x4	
#line 19
#define APMC_MCK_RDY				0x8	
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#define APMC_PCK0_RDY				0x100	
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#define APMC_PCK1_RDY				0x200	
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#define APMC_PCK2_RDY				0x400	
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#define APMC_PCK3_RDY				0x800	
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#define APMC_PCK4_RDY				0x1000	
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#define APMC_PCK5_RDY				0x2000	
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#define APMC_PCK6_RDY				0x4000	
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#define APMC_PCK7_RDY				0x8000	
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            END
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#define ST_BASE             0xFFFFF400      
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#define ST_WDRST			0x1			
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#define ST_RSTEN			0x10000 	
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#define ST_EXTEN			0x20000 	
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#define ST_PITS				0x1         
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#define ST_WDOVF			0x2			
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#define ST_RTTINC			0x4         
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#define ST_ALMS				0x8			
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		END
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#define PA0                  (1 << 0)
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#define PA1                  (1 << 1)
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#define PA2                  (1 << 2)
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#define PA3                  (1 << 3)
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#define PA4                  (1 << 4)
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#define PA5                  (1 << 5)
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#define PA6                  (1 << 6)
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#define PA7                  (1 << 7)
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#define PA8                  (1 << 8)
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#define PA9                  (1 << 9)
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#define PA10                 (1 << 10)
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#define PA11                 (1 << 11)
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#define PA12                 (1 << 12)
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#define PA13                 (1 << 13)
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#define PA14                 (1 << 14)
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#define PA15                 (1 << 15)
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#define PA16                 (1 << 16)
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#define PA17                 (1 << 17)
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#define PA18                 (1 << 18)
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#define PA19                 (1 << 19)
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#define PA20                 (1 << 20)
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#define PA21                 (1 << 21)
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#define PA22                 (1 << 22)
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#define PA23                 (1 << 23)
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#define PA24                 (1 << 24)
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#define PA25                 (1 << 25)
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#define PA26                 (1 << 26)
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#define PA27                 (1 << 27)
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#define PA28                 (1 << 28)
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#define PA29                 (1 << 29)
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#define PA30                 (1 << 30)
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#define PA31                 (1 << 31)
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                END
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                END
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#line 20




BeginFiqHandler


	ldr         r9,  [r8, 0x20]

	mov         r10, sp	
	ands        r11, r9,  UDP_EP0INT
	ldmneia     r10,  {r11, r12, pc}


	ands        r11, r9,  UDP_EP1INT
	ldmneia     r10,  {r11, r12, pc}


	ands        r11, r9,  UDP_EP2INT
	ldmneia     r10,  {r11, r12, pc}

	

	b           dma_notify_isr
	





dma_achieve_fiq

	sub         pc, lr, 4




dma_notify_isr

	ldr         r9, =AIC_BASE
	mov         r10, AIC_UDP_ISR
	str         r10, [r9, 324]     


	str         r10, [r9, 328]     
 

	sub         pc, lr, 4
	


fiq_udp_ep0
	ldr         r9,  [r8, 0x60]	
#line 73
fiq_udp_ep0_rcv
#line 73

#line 73
	ands        r10, r9,  UDP_RCV_DATA_BANK0 | UDP_RCV_DATA_BANK1
#line 73
	bne         fiq_udp_ep0_rcvexit
#line 73

#line 73

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	stmfd       sp!, {r9, r10, lr}
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	bl          dma_rx
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	ldmfd       sp!, {r9, r10, lr}
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#line 73

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	eor         r10, r10, r9
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	ldr         r10,  [r8, 0x60]
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	tst         r12, 1
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	bne         dma_achieve_fiq 
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	beq         dma_notify_isr 
#line 73

#line 73
fiq_udp_ep0_rcvexit
#line 73

#line 73

	ldr         r9,  [r8, 0x60]	
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fiq_udp_ep0_tx
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	ands        r10, r9,  UDP_TXCOMPLETE
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	bne         fiq_udp_ep0_txexit
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#line 75

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	stmfd       sp!, {r9, r10, lr}
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	bl          dma_tx
#line 75
	ldmfd       sp!, {r9, r10, lr}
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	eor         r10, r10, r9
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	ldr         r10,  [r8, 0x60]
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	tst         r12, 1
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	bne         dma_achieve_fiq 
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	beq         dma_notify_isr 
#line 75

#line 75
fiq_udp_ep0_txexit
#line 75

	b           dma_notify_isr
	
fiq_udp_ep1
	ldr         r9,  [r8, 0x64]
#line 80
fiq_udp_ep1_rcv
#line 80

#line 80
	ands        r10, r9,  UDP_RCV_DATA_BANK0 | UDP_RCV_DATA_BANK1
#line 80
	bne         fiq_udp_ep1_rcvexit
#line 80

#line 80

#line 80
	stmfd       sp!, {r9, r10, lr}
#line 80
	bl          dma_rx
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	ldmfd       sp!, {r9, r10, lr}
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#line 80

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	eor         r10, r10, r9
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	ldr         r10,  [r8, 0x60]
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#line 80

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	tst         r12, 1
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	bne         dma_achieve_fiq 
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	beq         dma_notify_isr 
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fiq_udp_ep1_rcvexit
#line 80

#line 80

	b           dma_notify_isr
	
fiq_udp_ep2
	ldr         r9,  [r8, 0x68]
#line 85
fiq_udp_ep2_rcv
#line 85

#line 85
	ands        r10, r9,  UDP_RCV_DATA_BANK0 | UDP_RCV_DATA_BANK1
#line 85
	bne         fiq_udp_ep2_rcvexit
#line 85

#line 85

#line 85
	stmfd       sp!, {r9, r10, lr}
#line 85
	bl          dma_rx
#line 85
	ldmfd       sp!, {r9, r10, lr}
#line 85

#line 85

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	eor         r10, r10, r9
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	ldr         r10,  [r8, 0x60]
#line 85

#line 85

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	tst         r12, 1
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	bne         dma_achieve_fiq 
#line 85
	beq         dma_notify_isr 
#line 85

#line 85
fiq_udp_ep2_rcvexit
#line 85

#line 85

	b           dma_notify_isr


dma_rx


	mov         r9, r9, LSR 16
	cmp         r9, r12
	movge       r9, r12
	


	add         r12, r12, r9
	str         r12, [r10, 0]

	add         r12, r11, r9
	str         r11, [r10, 1]
	

#line 105
	
#line 105

#line 105
	movs        r10, r9, LSR 7
#line 105
	beq         dma_rxloop64
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dma_rxloop128
#line 105
#line 105

#line 105

#line 105

#line 105

#line 105
	.rept        128
#line 105
	ldrb        r12, [r8] 
#line 105
	strb        r12, [r11],1
#line 105
	.endr
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#line 105

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	subs        r10, r10, 1
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	beq         dma_rxloop128
#line 105
	and         r9, r9, 0x7F
#line 105
	
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	movs        r10, r9, LSR 6
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	beq         dma_rxloop32
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dma_rxloop64
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	.rept        64
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	ldrb        r12, [r8] 
#line 105
	strb        r12, [r11],1
#line 105
	.endr
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	subs        r10, r10, 1
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	beq         dma_rxloop64
#line 105
	and         r9, r9, 0x3F
#line 105
	
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	movs        r10, r9, LSR 5
#line 105
	beq         dma_rxloop8
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dma_rxloop32
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#line 105

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#line 105

#line 105
	.rept        32
#line 105
	ldrb        r12, [r8] 
#line 105
	strb        r12, [r11],1
#line 105
	.endr
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	subs        r10, r10, 1
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	beq         dma_rxloop32
#line 105
	and         r9, r9, 0x1F
#line 105

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	movs        r10, r9, LSR 3
#line 105
	beq         dma_rxloop1
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dma_rxloop8
#line 105
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#line 105

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#line 105

#line 105
	.rept        8
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	ldrb        r12, [r8] 
#line 105
	strb        r12, [r11],1
#line 105
	.endr
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	subs        r10, r10, 1
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	beq         dma_rxloop8
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	and         r9, r9, 0x7
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	beq         dma_rxexit	
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dma_rxloop1
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	.rept        1
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	ldrb        r12, [r8] 
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	strb        r12, [r11],1
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	.endr
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	subs        r9, r9, 1
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	beq         dma_rxloop1
#line 105
	
#line 105
dma_rxexit	
#line 105



	ret

dma_tx


	mov         r9, r9, LSR 16
	cmp         r9, r12
	movge       r9, r12
	


	sub         r12, r12, r9
	str         r12, [r10, 0]

	add         r12, r11, r9
	str         r11, [r10, 1]
	

#line 126
	
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	movs        r10, r9, LSR 7
#line 126
	beq         dma_txloop64
#line 126
dma_txloop128
#line 126
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#line 126

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#line 126
	.rept       128
#line 126
	ldrb        r12, [r8], 1 
#line 126
	strb        r12, [r11]
#line 126
	.endr
#line 126

#line 126

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	subs        r10, r10, 1
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	beq         dma_txloop128
#line 126
	and         r9, r9, 0x7F
#line 126
	
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	movs        r10, r9, LSR 6
#line 126
	beq         dma_txloop32
#line 126
dma_txloop64
#line 126
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#line 126

#line 126

#line 126

#line 126
	.rept       64
#line 126
	ldrb        r12, [r8], 1 
#line 126
	strb        r12, [r11]
#line 126
	.endr
#line 126

#line 126

#line 126
	subs        r10, r10, 1
#line 126
	beq         dma_txloop64
#line 126
	and         r9, r9, 0x3F
#line 126
	
#line 126

#line 126
	movs        r10, r9, LSR 5
#line 126
	beq         dma_txloop8
#line 126
dma_txloop32
#line 126
#line 126

#line 126

#line 126

#line 126

#line 126
	.rept       32
#line 126
	ldrb        r12, [r8], 1 
#line 126
	strb        r12, [r11]
#line 126
	.endr
#line 126

#line 126

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	subs        r10, r10, 1
#line 126
	beq         dma_txloop32
#line 126
	and         r9, r9, 0x1F
#line 126

#line 126

#line 126
	movs        r10, r9, LSR 3
#line 126
	beq         dma_txloop1
#line 126
dma_txloop8
#line 126
#line 126

#line 126

#line 126

#line 126

#line 126
	.rept       8
#line 126
	ldrb        r12, [r8], 1 
#line 126
	strb        r12, [r11]
#line 126
	.endr
#line 126

#line 126

#line 126
	subs        r10, r10, 1
#line 126
	beq         dma_txloop8
#line 126
	and         r9, r9, 0x7
#line 126

#line 126

#line 126
	beq         dma_txexit	
#line 126
dma_txloop1
#line 126
#line 126

#line 126

#line 126

#line 126

#line 126
	.rept       1
#line 126
	ldrb        r12, [r8], 1 
#line 126
	strb        r12, [r11]
#line 126
	.endr
#line 126

#line 126

#line 126
	subs        r9, r9, 1
#line 126
	beq         dma_txloop1
#line 126
	
#line 126
dma_txexit	
#line 126

	ret


	END
12

lib_udp.paf.arm - 源码说明

本页面展示了「ARM9200开发板的ROM boot程序源码1.0」中的 lib_udp.paf.arm 源码文件，采用 ARM 编程语言编写，共 2,376 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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