twi.h

ARM9200开发板的ROM boot程序源码1.0

//*---------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name           : TWI.h
//* Object              : Two Wire Definition File
//*
//* 1.0 02/23/01 HI    : Creation
//*---------------------------------------------------------------------------
#ifndef twi_h
#define twi_h

/*---------------------------------------*/
/*  Inter Integrated Circuit Controled   */
/*---------------------------------------*/

typedef struct _AT91S_TWI
{
    at91_reg	TWI_CR ;  			/* Control Register */
    at91_reg	TWI_MMR ;  			/* Master Mode Register */
    at91_reg	TWI_SMR ;  			/* Slave Mode Register */
    at91_reg	TWI_IADR ;	  		/* slave Internal Address Register */
    at91_reg	TWI_CWGR ;  		/* clock waveform Generator Register */
    at91_reg	Reserved[3];		/* 0x14,0x18,0x1C */
    at91_reg	TWI_SR ;  			/* Status Register */
    at91_reg	TWI_IER ;  			/* Interrupt Enable Register */
    at91_reg	TWI_IDR ;  			/* Interrupt Disable Register */
    at91_reg	TWI_IMR ;  			/* Interrupt Mask Register */
    at91_reg	TWI_RHR ;  			/* Receive Holding Register */
    at91_reg	TWI_THR ;  			/* Transmit Holding Register */
}AT91S_TWI, *AT91PS_TWI ;


/*------------------------------------------------------*/
/* I2C Control Registers Bits Definition                  */
/*------------------------------------------------------*/
#define		TWI_START				0x1			/* Start frame bit */
#define		TWI_STOP				0x2			/* Stop frame bit */
#define		TWI_MSEN				0x4			/* Master Xfer Enable */
#define		TWI_MSDIS				0x8			/* Master Xfer DISable */
#define		TWI_SVEN				0x10		/* Slave Xfer Enable */
#define		TWI_SVDIS				0x20		/* Slave Xfer DISable*/
#define		TWI_SWRST				0x80		/* Software Reset */

/*------------------------------------------------------*/
/* I2C Master Mode Registers Bits Definition                  */
/*------------------------------------------------------*/
#define		TWI_IADRSZ					0x0300			/* Internal Device Address Size */
#define		TWI_IADRSZ_NOINTADDR		0x0000			/* No Internal Device Address */
#define		TWI_IADRSZ_1INT_ADDR		0x0100			/* 1 Byte Internal Device Address  */
#define		TWI_IADRSZ_2INT_ADDR		0x0200			/* 2 Byte Internal Device Address  */
#define		TWI_IADRSZ_3INT_ADDR		0x0300			/* 3 Byte Internal Device Address */

#define		TWI_MREAD					0x1000			/* Master Read Direction 0=Wr 1=Rd */
#define		TWI_MWRITE					0				/* Master Write Direction 0=Wr 1=Rd */
#define		TWI_DADR					0xFF0000		/* Device Address */

/*------------------------------------------------------*/
/* I2C Slave Mode Registers Bits Definition             */
/*------------------------------------------------------*/
#define		TWI_SADR				0xFF0000		/* Slave Device Address when Device is in Slave Mode */

//*------------------------------------------------------*/
//* I2C Internal Address Registers Bits Definition       */
//*------------------------------------------------------*/
//*	#define		TWI_IADR				0xFFFFFF
/* 	Internal address */
//*
//*------------------------------------------------------*/
//* I2C Clock Waveform Generator Registers Bits Definition */
//*
//*                   CKDIV
//* Tlow = (CLDIV+3)x2     xTMCLK
//*
//*                    CKDIV
//* Thigh = (CHDIV+3)x2     xTMCLK
//*------------------------------------------------------*/

#define		TWI_CLDIV				0xFF			/* Clock Low Divider */
#define		TWI_CHDIV				0xFF00			/* Clock High Divider */
#define		TWI_CKDIV				0x70000			/* Clock Divider */

/*------------------------------------------------------*/
/* I2C Status Registers Bits Definition					*/
/* Valid for IER/IDR/IMR register as well				*/
/*------------------------------------------------------*/
#define		TWI_TXCOMP				0x00000001			/* Transmission Complete			*/
#define		TWI_RXRDY				0x00000002			/* Receive Holding register ready	*/
#define		TWI_TXRDY				0x00000004			/* Transmit Holding register ready	*/
#define		TWI_SVDIR				0x00000008			/* Slave direction					*/
#define		TWI_SVACC				0x00000010		/* Slave Access						*/
#define		TWI_ARBLST				0x00000020		/* Arbitration lost					*/
#define		TWI_OVRE				0x00000040		/* Over Run Error					*/
#define		TWI_UNRE				0x00000080		/* Under Run Error					*/
#define		TWI_NACK				0x00000100		/* Not Acknowledged					*/
#define		TWI_ERROR			    ( TWI_NACK | TWI_UNRE | TWI_OVRE )

#endif //* twi_h