ebic.inc

来自「ARM9200开发板的ROM boot程序源码1.0」· INC 代码 · 共 64 行

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File Name            : ebic.inc
;- Object               : Assembler External Bus Interface Definition File.
;-
;- 1.0 22/03/01 ED      : Creation
;------------------------------------------------------------------------------

            INCLUDE     periph/smc/smc.inc
            INCLUDE     periph/sdramc/sdramc.inc
            INCLUDE     periph/bfc/bfc.inc

;------------------------------------------------------------
; External Bus Interface User Interface Structure Definition
;------------------------------------------------------------

                ^       0
EBIC_CSA	#	4	;- Chip Select Assignment
EBIC_CR		#	4	;- Configuration Register
		#	4*2	;- Reserved
EBIC_SMC_MR	#	4*8	;- Chip Select Registers
		#	4*8	;- Reserved
EBIC_SDRC_MR	#	4	;- Mode Register
EBIC_SDRC_TR	#	4	;- Refresh Timer Register
EBIC_SDRC_CR	#	4	;- Configuration Register
EBIC_SDRC_SRR	#	4	;- Self Refresh Command Register
EBIC_SDRC_LPR	#	4	;- Low Power Command Register
EBIC_SDRC_IER	#	4	;- Interrupt Enable Register
EBIC_SDRC_IDR	#	4	;- Interrupt Disable Register
EBIC_SDRC_IMR	#	4	;- Interrupt Mask Register
EBIC_SDRC_ISR	#	4	;- Interrupt Status Register
		#	4*7	;- Reserved
EBIC_BFC_MR	#	4	;- Mode Register

;-------------------------------------
;- EBIC_CSAR : Chip Select Assignment
;-------------------------------------

EBIC_CS0_SMC		EQU	0x0		;- EBIC Chip Select 0 assigned to the SMC
EBIC_CS0_BFC		EQU	0x1		;- EBIC Chip Select 0 assigned to the BFC

EBIC_CS1_SMC		EQU	0x0		;- EBIC Chip Select 1 assigned to the SMC
EBIC_CS1_SDRAMC		EQU	0x2		;- EBIC Chip Select 1 assigned to the SDRAMC

;-----------------------------------
;- EBIC_CR : Configuration Register
;-----------------------------------

EBIC_PU_EN		EQU	0x0		;- EBIC Data Pulled-up
EBIC_PU_DIS		EQU	0x1		;- EBIC Data not Pulled-up

EBIC_HOLD_DIS		EQU	0x0		;- EBIC Bus Sharing Feature Disabled
EBIC_HOLD_EN		EQU	0x2		;- EBIC Bus Sharing Feature Enabled


                END