smc.h

ARM9200开发板的ROM boot程序源码1.0

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : smc.h
//* Object              : Static Memory Controller Header File
//*
//* 1.0 22/03/01 ED     : Creation
//*----------------------------------------------------------------------------

#ifndef smc_h
#define smc_h

#include    "periph/stdc/std_c.h"

/*--------------------------------------------------------------*/
/* Static Memory Controller User Interface Structure Definition */
/*--------------------------------------------------------------*/

typedef struct _AT91S_SMC
{
    at91_reg		SMC_CSR[8] ;		/* Chip Select Registers */
} AT91S_SMC, *AT91PS_SMC ;

/*---------------------------------*/
/* SMC_CSR : Chip Select Registers */
/*---------------------------------*/

#define	SMC_NWS_MASK			0x7F		/* SMC Number of Wait States Definition */

#define	SMC_WSEN				0x80		/* SMC Wait States ENable Bit */

#define	SMC_TDF_MASK			0xF00		/* SMC Number of Data Float Time Definition */
#define	SMC_TDF_SHIFT			0x8			/* Logical Left Shift to be applied for TDF */

#define	SMC_BAT					0x1000		/* SMC Byte Access Type Bit */
#define	SMC_BAT_BYTE_WRITE		0x0			/* SMC Byte Write Access Type */
#define	SMC_BAT_BYTE_SELECT		0x1000		/* SMC Byte Select Access Type */

#define	SMC_DBW_MASK			0x6000		/* SMC Data Bus Width Definition */
#define	SMC_DBW_16				0x2000		/* SMC 16-bit Data Bus Width */
#define	SMC_DBW_8				0x4000		/* SMC 8-bit Data Bus Width */

#define	SMC_DRP					0x8000		/* SMC Data Read Protocol Definition */
#define	SMC_DRP_STANDARD		0x0			/* SMC Standard Read Protocol */
#define	SMC_DRP_EARLY			0x8000		/* SMC Early Read Protocol */

#define	SMC_ACSS_MASK			0x30000		/* SMC Address to Chip Select Setup Definition */
#define	SMC_ACSS_0				0x0			/* 0 Cycle inserted */
#define	SMC_ACSS_1				0x10000		/* 1 Cycle inserted */
#define	SMC_ACSS_2				0x20000		/* 2 Cycles inserted */
#define	SMC_ACSS_3				0x30000		/* 3 Cycles inserted */

#define	SMC_RWSETUP_MASK		0x7000000	/* SMC Read and Write Signal Setup Time Definition */
#define	SMC_RWSETUP_0			0x0			/* RWSETUP = 0 */
#define	SMC_RWSETUP_1			0x1000000	/* 1 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_2			0x2000000	/* 2 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_3			0x3000000	/* 3 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_4			0x4000000	/* 4 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_5			0x5000000	/* 5 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_6			0x6000000	/* 6 + 1/2 Setup Cycle inserted */
#define	SMC_RWSETUP_7			0x7000000	/* 7 + 1/2 Setup Cycle inserted */

#define	SMC_RWHOLD_MASK			0x70000000	/* SMC Read and Write Signal Hold Time Definition */
#define	SMC_RWHOLD_0			0x0			/* RWHOLD = 0 */
#define	SMC_RWHOLD_1			0x10000000	/* 1 Hold Cycle inserted */
#define	SMC_RWHOLD_2			0x20000000	/* 2 Hold Cycle inserted */
#define	SMC_RWHOLD_3			0x30000000	/* 3 Hold Cycle inserted */
#define	SMC_RWHOLD_4			0x40000000	/* 4 Hold Cycle inserted */
#define	SMC_RWHOLD_5			0x50000000	/* 5 Hold Cycle inserted */
#define	SMC_RWHOLD_6			0x60000000	/* 6 Hold Cycle inserted */
#define	SMC_RWHOLD_7			0x70000000	/* 7 Hold Cycle inserted */

#endif /* smc_h */