smc.inc

ARM9200开发板的ROM boot程序源码1.0

;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;------------------------------------------------------------------------------
;- File Name            : smc.inc
;- Object               : Assembler Static Memory Controller Definition File.
;-
;- 1.0 22/03/01 ED      : Creation
;------------------------------------------------------------------------------

;--------------------------------------------------------------
; Static Memory Controller User Interface Structure Definition
;--------------------------------------------------------------

                ^       0
SMC_MR		#	4*8	;- Chip Select Registers

;----------------------------------
;- SMC_CSR : Chip Select Registers
;----------------------------------

SMC_NWS_MASK		EQU	0x7F		;- SMC Number of Wait States Definition

SMC_WSEN		EQU	0x80		;- SMC Wait States ENable Bit

SMC_TDF_MASK		EQU	0xF00		;- SMC Number of Data Float Time Definition
SMC_TDF_SHIFT		EQU	0x8		;- Logical Left Shift to be applied for TDF

SMC_BAT			EQU	0x1000		;- SMC Byte Access Type Bit
SMC_BAT_BYTE_WRITE	EQU	0x0		;- SMC Byte Write Access Type
SMC_BAT_BYTE_SELECT	EQU	0x1000		;- SMC Byte Select Access Type

SMC_DBW_MASK		EQU	0x6000		;- SMC Data Bus Width Definition
SMC_DBW_16		EQU	0x2000		;- SMC 16-bit Data Bus Width
SMC_DBW_8		EQU	0x4000		;- SMC 8-bit Data Bus Width

SMC_DRP			EQU	0x8000		;- SMC Data Read Protocol Definition
SMC_DRP_STANDARD	EQU	0x0		;- SMC Standard Read Protocol
SMC_DRP_EARLY		EQU	0x8000		;- SMC Early Read Protocol

SMC_ACSS_MASK		EQU	0x30000		;- SMC Address to Chip Select Setup Definition
SMC_ACSS_0		EQU	0x0		;- 0 Cycle inserted
SMC_ACSS_1		EQU	0x10000		;- 1 Cycle inserted
SMC_ACSS_2		EQU	0x20000		;- 2 Cycles inserted
SMC_ACSS_3		EQU	0x30000		;- 3 Cycles inserted

SMC_RWSETUP_MASK	EQU	0x7000000	;- SMC Read and Write Signal Setup Time Definition
SMC_RWSETUP_0		EQU	0x0		;- RWSETUP = 0
SMC_RWSETUP_1		EQU	0x1000000	;- 1 + 1/2 Setup Cycle inserted
SMC_RWSETUP_2		EQU	0x2000000	;- 2 + 1/2 Setup Cycle inserted
SMC_RWSETUP_3		EQU	0x3000000	;- 3 + 1/2 Setup Cycle inserted
SMC_RWSETUP_4		EQU	0x4000000	;- 4 + 1/2 Setup Cycle inserted
SMC_RWSETUP_5		EQU	0x5000000	;- 5 + 1/2 Setup Cycle inserted
SMC_RWSETUP_6		EQU	0x6000000	;- 6 + 1/2 Setup Cycle inserted
SMC_RWSETUP_7		EQU	0x7000000	;- 7 + 1/2 Setup Cycle inserted

SMC_RWHOLD_MASK		EQU	0x70000000	;- SMC Read and Write Signal Hold Time Definition
SMC_RWHOLD_0		EQU	0x0		;- RWHOLD = 0
SMC_RWHOLD_1		EQU	0x10000000	;- 1 Hold Cycle inserted
SMC_RWHOLD_2		EQU	0x20000000	;- 2 Hold Cycle inserted
SMC_RWHOLD_3		EQU	0x30000000	;- 3 Hold Cycle inserted
SMC_RWHOLD_4		EQU	0x40000000	;- 4 Hold Cycle inserted
SMC_RWHOLD_5		EQU	0x50000000	;- 5 Hold Cycle inserted
SMC_RWHOLD_6		EQU	0x60000000	;- 6 Hold Cycle inserted
SMC_RWHOLD_7		EQU	0x70000000	;- 7 Hold Cycle inserted


                END