clock16.vhd

来自「eda 开发数字钟的设计具体编程代码和开发流程与设计图」· VHDL 代码 · 共 39 行

--*************************************************************************************--
--Colour Sort Machine/Fifteen dividing clock module V1.0/01.11.30
--EIST Department,Nankai University
--Function part/clockall/15-dividing clock
--Src file:clock15.vhd
--Serial number:005
--2001----2002
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock16 is
  port(clkin:in std_logic;     
       clkout:out std_logic  
       );
end entity;

architecture arc of clock16 is
begin
 process(clkin) 
  variable count:integer range 0 to 15;
  begin
    if (clkin'event and clkin='1') then
    --	if count>=15 then
    --		count:=0;
    --	else
    		count:=count+1;	
    --	end if;
    	
    	case count is
    		when 0 to 7 =>clkout<='0';
    		when others =>clkout<='1';
    	end case;    		
    end if;
  end process;
end arc;