clkv.vhd

eda 开发数字钟的设计具体编程代码和开发流程与设计图

--*************************************************************************************--
--Colour Sort Machine/Test circuit/Clk_v module V1.0/01.12.18
--EIST Department,Nankai University
--Debug part/debug/clkv
--Src file:clkv.vhd
--Serial number:014
--2001----2002
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clkv is
       port(clkin:in std_logic;
			clkout:out std_logic
            );
end clkv;

architecture arc of clkv is
begin
  process (clkin)
    variable count:std_logic_vector(13 downto 0);
  begin
    if clkin'event and clkin='1' then
       count:=count+1;
    end if;
    clkout<=count(9);
  end process;
end arc;