clock5.vhd

来自「eda 开发数字钟的设计具体编程代码和开发流程与设计图」· VHDL 代码 · 共 45 行

--*************************************************************************************--
--Colour Sort Machine/Five dividing clock module V1.0/01.11.30
--EIST Department,Nankai University
--Function part/clockall/5-dividing clock
--Src file:clock5.vhd
--Serial number:004
--2001----2002
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock5 is
  port(clk:in std_logic;  
       clkout:out std_logic
       );
end entity;

architecture arc of clock5 is
begin
 process(clk)  
  variable count:std_logic_vector(2 downto 0);
  begin
    if (clk'event and clk='1') then
       case count is
          when "000"=>count:="001";    --Gray codeing counter
          when "001"=>count:="011";
          when "011"=>count:="111";
          when "111"=>count:="110";
          when "110"=>count:="000";
          when others=>count:="000";
        end case;
    end if;

   case count is
     when "000"=>clkout<='0';
     when "001"=>clkout<='0';
     when "011"=>clkout<='1';
     when "111"=>clkout<='1';
     when "110"=>clkout<='1';
     when others=>clkout<='0';
   end case;
  end process;
end arc;