📄 clock15.vhd
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--*************************************************************************************--
--Colour Sort Machine/Fifteen dividing clock module V1.0/01.11.30
--EIST Department,Nankai University
--Function part/clockall/15-dividing clock
--Src file:clock15.vhd
--Serial number:005
--2001----2002
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock15 is
port(clk:in std_logic;
clkout:out std_logic
);
end entity;
architecture arc of clock15 is
begin
process(clk)
variable count:std_logic_vector(3 downto 0);
begin
if (clk'event and clk='1') then
case count is
when "0000"=>count:="0001"; --Gray coding counter
when "0001"=>count:="0011";
when "0011"=>count:="0010";
when "0010"=>count:="0110";
when "0110"=>count:="0111";
when "0111"=>count:="0101";
when "0101"=>count:="0100";
when "0100"=>count:="1100";
when "1100"=>count:="1101";
when "1101"=>count:="1111";
when "1111"=>count:="1110";
when "1110"=>count:="1010";
when "1010"=>count:="1011";
when "1011"=>count:="1001";
when "1001"=>count:="0000"; --if 1001 change 1000 or 0001, count is always 0.
when others=>count:="0000";
end case;
end if;
case count is
when "0000"=>clkout<='0';
when "0001"=>clkout<='0';
when "0011"=>clkout<='0';
when "0010"=>clkout<='0';
when "0110"=>clkout<='0';
when "0111"=>clkout<='0';
when "0101"=>clkout<='0';
when "0100"=>clkout<='1';
when "1100"=>clkout<='1';
when "1101"=>clkout<='1';
when "1111"=>clkout<='1';
when "1110"=>clkout<='1';
when "1010"=>clkout<='1';
when "1011"=>clkout<='1';
when "1001"=>clkout<='1'; --if 1001 change 1000 or 0001, count is always 0.
when others=>clkout<='0';
end case;
end process;
end arc;
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