all_01.map.rpt

eda 开发数字钟的设计具体编程代码和开发流程与设计图

; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                       ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+
; all_01.bdf                       ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf    ;
; HEX2DEC.vhd                      ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd   ;
; CLOCK40.vhd                      ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd   ;
; CLOCK_SPK.vhd                    ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd ;
; CYC_PLL.tdf                      ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CYC_PLL.tdf   ;
; altpll.inc                       ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/altpll.inc                             ;
; altpll.tdf                       ; yes             ; Megafunction                       ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf                             ;
; aglobal60.inc                    ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc                          ;
; stratix_pll.inc                  ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc                        ;
; stratixii_pll.inc                ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc                      ;
; cycloneii_pll.inc                ; yes             ; Other                              ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc                      ;
; CLOCK2.vhd                       ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2.vhd    ;
; CLOCK2500.vhd                    ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2500.vhd ;
; clockall.gdf                     ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf  ;
; CLOCK150.vhd                     ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK150.vhd  ;
; CLOCK16.vhd                      ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK16.vhd   ;
; DEBUGLED.vhd                     ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd  ;
; hhmmss.vhd                       ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd    ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Aug 05 09:01:46 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off all_01 -c all_01
Info: Found 1 design units, including 1 entities, in source file all_01.bdf
    Info: Found entity 1: all_01
Info: Found 2 design units, including 1 entities, in source file HEX2DEC.vhd
    Info: Found design unit 1: HEX2DEC-arc
    Info: Found entity 1: HEX2DEC
Info: Found 2 design units, including 1 entities, in source file CLOCK40.vhd
    Info: Found design unit 1: clock40-arc
    Info: Found entity 1: clock40
Info: Elaborating entity "all_01" for the top level hierarchy
Warning: Using design file CLOCK_SPK.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock_spk-arc
    Info: Found entity 1: clock_spk
Info: Elaborating entity "CLOCK_SPK" for hierarchy "CLOCK_SPK:17"
Info: Elaborating entity "clock40" for hierarchy "clock40:inst3"
Warning: Using design file CYC_PLL.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: CYC_PLL
Info: Elaborating entity "CYC_PLL" for hierarchy "CYC_PLL:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "CYC_PLL:inst|altpll:altpll_component"
Info: Elaborated megafunction instantiation "CYC_PLL:inst|altpll:altpll_component"
Warning: Using design file CLOCK2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock2-arc
    Info: Found entity 1: clock2
Info: Elaborating entity "CLOCK2" for hierarchy "CLOCK2:inst2"
Warning: Using design file CLOCK2500.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock2500-arc
    Info: Found entity 1: clock2500
Info: Elaborating entity "CLOCK2500" for hierarchy "CLOCK2500:14"
Warning: Using design file clockall.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: clockall
Info: Elaborating entity "clockall" for hierarchy "clockall:9"
Warning: Using design file CLOCK150.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock150-arc
    Info: Found entity 1: clock150
Info: Elaborating entity "CLOCK150" for hierarchy "clockall:9|CLOCK150:29"
Warning: Using design file CLOCK16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock16-arc
    Info: Found entity 1: clock16
Info: Elaborating entity "CLOCK16" for hierarchy "clockall:9|CLOCK16:27"
Warning: Using design file DEBUGLED.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: debugled-arc
    Info: Found entity 1: debugled
Info: Elaborating entity "DEBUGLED" for hierarchy "DEBUGLED:10"
Info: Elaborating entity "HEX2DEC" for hierarchy "HEX2DEC:inst4"
Warning: Using design file hhmmss.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: hhmmss-arc
    Info: Found entity 1: hhmmss
Info: Elaborating entity "hhmmss" for hierarchy "hhmmss:inst8"
Error (10028): Can't resolve multiple constant drivers for net "var_hh[7]" at hhmmss.vhd(54) File: C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd Line: 54
Error (10029): Constant driver at hhmmss.vhd(71) File: C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd Line: 71
Error: Can't elaborate user hierarchy "hhmmss:inst8"
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 9 warnings
    Error: Processing ended: Sun Aug 05 09:01:48 2007
    Error: Elapsed time: 00:00:03