all_01.hier_info

eda 开发数字钟的设计具体编程代码和开发流程与设计图

|all_01
SPK <= CLOCK_SPK:17.clkout
CLK20M => CYC_PLL:inst.inclk0
KEY[1] => CLOCK_SPK:17.sound[1]
KEY[2] => CLOCK_SPK:17.sound[2]
KEY[3] => CLOCK_SPK:17.sound[3]
KEY[4] => CLOCK_SPK:17.sound[4]
KEY[5] => CLOCK_SPK:17.sound[5]
KEY[6] => CLOCK_SPK:17.sound[6]
KEY[7] => CLOCK_SPK:17.sound[7]
KEY[8] => ~NO_FANOUT~
KEY[9] => ~NO_FANOUT~
KEY[10] => hhmmss:inst8.set_ss
KEY[11] => hhmmss:inst8.set_mm
KEY[12] => hhmmss:inst8.set_hh
EXA_IO1 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
WORKING_LED <= CLOCK2:inst2.clkout
FP_DATA_DIR <= <GND>
DIG[1] <= DEBUGLED:10.digit[0]
DIG[2] <= DEBUGLED:10.digit[1]
DIG[3] <= DEBUGLED:10.digit[2]
DIG[4] <= DEBUGLED:10.digit[3]
DIG[5] <= DEBUGLED:10.digit[4]
DIG[6] <= DEBUGLED:10.digit[5]
EX_D[1] <= LEDFLASH:12.LED[1]
EX_D[2] <= LEDFLASH:12.LED[2]
EX_D[3] <= LEDFLASH:12.LED[3]
EX_D[4] <= LEDFLASH:12.LED[4]
EX_D[5] <= LEDFLASH:12.LED[5]
EX_D[6] <= LEDFLASH:12.LED[6]
EX_D[7] <= LEDFLASH:12.LED[7]
EX_D[8] <= LEDFLASH:12.LED[8]
EX_D[9] <= LEDFLASH:12.LED[9]
EX_D[10] <= LEDFLASH:12.LED[10]
EX_D[11] <= LEDFLASH:12.LED[11]
EX_D[12] <= LEDFLASH:12.LED[12]
SEG[1] <= DEBUGLED:10.seg[0]
SEG[2] <= DEBUGLED:10.seg[1]
SEG[3] <= DEBUGLED:10.seg[2]
SEG[4] <= DEBUGLED:10.seg[3]
SEG[5] <= DEBUGLED:10.seg[4]
SEG[6] <= DEBUGLED:10.seg[5]
SEG[7] <= DEBUGLED:10.seg[6]
SEG[8] <= DEBUGLED:10.seg[7]


|all_01|CLOCK_SPK:17
clkin => clkout~reg0.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clkin => count[4].CLK
clkin => count[5].CLK
clkin => count[6].CLK
clkin => count[7].CLK
clkin => count[8].CLK
clkin => count[9].CLK
clkin => count[10].CLK
clkin => count[11].CLK
sound[1] => Mux0.IN134
sound[1] => Mux1.IN13
sound[1] => Mux2.IN13
sound[1] => Mux3.IN13
sound[1] => Mux4.IN13
sound[1] => Mux5.IN13
sound[1] => Mux6.IN13
sound[1] => Mux7.IN13
sound[1] => Mux8.IN13
sound[1] => Mux9.IN13
sound[1] => Mux10.IN13
sound[1] => Mux11.IN13
sound[1] => Mux12.IN13
sound[2] => Mux0.IN133
sound[2] => Mux1.IN12
sound[2] => Mux2.IN12
sound[2] => Mux3.IN12
sound[2] => Mux4.IN12
sound[2] => Mux5.IN12
sound[2] => Mux6.IN12
sound[2] => Mux7.IN12
sound[2] => Mux8.IN12
sound[2] => Mux9.IN12
sound[2] => Mux10.IN12
sound[2] => Mux11.IN12
sound[2] => Mux12.IN12
sound[3] => Mux0.IN132
sound[3] => Mux1.IN11
sound[3] => Mux2.IN11
sound[3] => Mux3.IN11
sound[3] => Mux4.IN11
sound[3] => Mux5.IN11
sound[3] => Mux6.IN11
sound[3] => Mux7.IN11
sound[3] => Mux8.IN11
sound[3] => Mux9.IN11
sound[3] => Mux10.IN11
sound[3] => Mux11.IN11
sound[3] => Mux12.IN11
sound[4] => Mux0.IN131
sound[4] => Mux1.IN10
sound[4] => Mux2.IN10
sound[4] => Mux3.IN10
sound[4] => Mux4.IN10
sound[4] => Mux5.IN10
sound[4] => Mux6.IN10
sound[4] => Mux7.IN10
sound[4] => Mux8.IN10
sound[4] => Mux9.IN10
sound[4] => Mux10.IN10
sound[4] => Mux11.IN10
sound[4] => Mux12.IN10
sound[5] => Mux0.IN130
sound[5] => Mux1.IN9
sound[5] => Mux2.IN9
sound[5] => Mux3.IN9
sound[5] => Mux4.IN9
sound[5] => Mux5.IN9
sound[5] => Mux6.IN9
sound[5] => Mux7.IN9
sound[5] => Mux8.IN9
sound[5] => Mux9.IN9
sound[5] => Mux10.IN9
sound[5] => Mux11.IN9
sound[5] => Mux12.IN9
sound[6] => Mux0.IN129
sound[6] => Mux1.IN8
sound[6] => Mux2.IN8
sound[6] => Mux3.IN8
sound[6] => Mux4.IN8
sound[6] => Mux5.IN8
sound[6] => Mux6.IN8
sound[6] => Mux7.IN8
sound[6] => Mux8.IN8
sound[6] => Mux9.IN8
sound[6] => Mux10.IN8
sound[6] => Mux11.IN8
sound[6] => Mux12.IN8
sound[7] => Mux0.IN128
sound[7] => Mux1.IN7
sound[7] => Mux2.IN7
sound[7] => Mux3.IN7
sound[7] => Mux4.IN7
sound[7] => Mux5.IN7
sound[7] => Mux6.IN7
sound[7] => Mux7.IN7
sound[7] => Mux8.IN7
sound[7] => Mux9.IN7
sound[7] => Mux10.IN7
sound[7] => Mux11.IN7
sound[7] => Mux12.IN7
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|clock40:inst3
clkin => clkout~reg0.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clkin => count[4].CLK
clkin => count[5].CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|CYC_PLL:inst
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
c1 <= altpll:altpll_component.clk[1]


|all_01|CYC_PLL:inst|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|CLOCK2:inst2
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|CLOCK2:15
clkin => clkout~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|CLOCK2500:14
clkin => clkout~reg0.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clkin => count[4].CLK
clkin => count[5].CLK
clkin => count[6].CLK
clkin => count[7].CLK
clkin => count[8].CLK
clkin => count[9].CLK
clkin => count[10].CLK
clkin => count[11].CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|clockall:9
clk5k <= 23.DB_MAX_OUTPUT_PORT_TYPE
clk40k <= 15.DB_MAX_OUTPUT_PORT_TYPE
clk80k <= 13.DB_MAX_OUTPUT_PORT_TYPE
clk24M => CLOCK150:29.clkin
clk24M => CLOCK16:27.clkin
clk1_5M <= CLOCK16:27.clkout


|all_01|clockall:9|CLOCK150:29
clkin => clkout~reg0.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clkin => count[4].CLK
clkin => count[5].CLK
clkin => count[6].CLK
clkin => count[7].CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|clockall:9|CLOCK16:27
clkin => clkout~reg0.CLK
clkin => count[0].CLK
clkin => count[1].CLK
clkin => count[2].CLK
clkin => count[3].CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|DEBUGLED:10
din_l[0] => Mux16.IN2
din_l[1] => Mux15.IN2
din_l[2] => Mux14.IN2
din_l[3] => Mux13.IN2
din_l[4] => Mux16.IN3
din_l[5] => Mux15.IN3
din_l[6] => Mux14.IN3
din_l[7] => Mux13.IN3
din_m[0] => Mux16.IN4
din_m[1] => Mux15.IN4
din_m[2] => Mux14.IN4
din_m[3] => Mux13.IN4
din_m[4] => Mux16.IN5
din_m[5] => Mux15.IN5
din_m[6] => Mux14.IN5
din_m[7] => Mux13.IN5
din_r[0] => Mux16.IN6
din_r[1] => Mux15.IN6
din_r[2] => Mux14.IN6
din_r[3] => Mux13.IN6
din_r[4] => Mux16.IN7
din_r[5] => Mux15.IN7
din_r[6] => Mux14.IN7
din_r[7] => Mux13.IN7
clk => temp_seg[0].CLK
clk => temp_seg[1].CLK
clk => temp_seg[2].CLK
clk => temp_seg[3].CLK
clk => digit[0]~reg0.CLK
clk => digit[1]~reg0.CLK
clk => digit[2]~reg0.CLK
clk => digit[3]~reg0.CLK
clk => digit[4]~reg0.CLK
clk => digit[5]~reg0.CLK
clk => dig_cnt[0].CLK
clk => dig_cnt[1].CLK
clk => dig_cnt[2].CLK
clk => stay_cnt[0].CLK
clk => stay_cnt[1].CLK
seg[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <GND>
digit[0] <= digit[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
digit[1] <= digit[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
digit[2] <= digit[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
digit[3] <= digit[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
digit[4] <= digit[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
digit[5] <= digit[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|all_01|HEX2DEC:inst4
HEX[0] => LessThan0.IN16
HEX[0] => LessThan1.IN16
HEX[0] => LessThan2.IN16
HEX[0] => LessThan3.IN16
HEX[0] => LessThan4.IN16
HEX[0] => LessThan5.IN16
HEX[0] => DEC~7.DATAB
HEX[0] => DEC~15.DATAB
HEX[0] => DEC~23.DATAB
HEX[0] => DEC~31.DATAB
HEX[0] => DEC~39.DATAB
HEX[0] => DEC~47.DATAB
HEX[1] => LessThan0.IN15
HEX[1] => LessThan1.IN15
HEX[1] => Add0.IN14
HEX[1] => LessThan2.IN15
HEX[1] => LessThan3.IN15
HEX[1] => Add2.IN14
HEX[1] => LessThan4.IN15
HEX[1] => LessThan5.IN15
HEX[1] => Add4.IN14
HEX[1] => DEC~14.DATAB
HEX[1] => DEC~30.DATAB
HEX[1] => DEC~46.DATAB
HEX[2] => LessThan0.IN14
HEX[2] => LessThan1.IN14
HEX[2] => Add0.IN13
HEX[2] => LessThan2.IN14
HEX[2] => Add1.IN12
HEX[2] => LessThan3.IN14
HEX[2] => Add2.IN13
HEX[2] => LessThan4.IN14
HEX[2] => LessThan5.IN14
HEX[2] => Add4.IN13
HEX[2] => DEC~13.DATAB
HEX[2] => DEC~45.DATAB
HEX[3] => LessThan0.IN13
HEX[3] => LessThan1.IN13
HEX[3] => Add0.IN12
HEX[3] => LessThan2.IN13
HEX[3] => Add1.IN11
HEX[3] => LessThan3.IN13
HEX[3] => Add2.IN12
HEX[3] => LessThan4.IN13
HEX[3] => Add3.IN10
HEX[3] => LessThan5.IN13
HEX[3] => Add4.IN12
HEX[3] => DEC~44.DATAB