all_01.fit.qmsg

eda 开发数字钟的设计具体编程代码和开发流程与设计图

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "KEY\[10\] Global clock " "Info: Automatically promoted signal \"KEY\[10\]\" to use Global clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "KEY\[10\] " "Info: Pin \"KEY\[10\]\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[10] } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "KEY\[11\] Global clock " "Info: Automatically promoted signal \"KEY\[11\]\" to use Global clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "KEY\[11\] " "Info: Pin \"KEY\[11\]\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[11] } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "KEY\[12\] Global clock " "Info: Automatically promoted signal \"KEY\[12\]\" to use Global clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "KEY\[12\] " "Info: Pin \"KEY\[12\]\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KEY[12] } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 CYC_PLL:inst\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"CYC_PLL:inst\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "CYC_PLL.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CYC_PLL.tdf" 45 2 0 } } { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { -136 472 744 40 "inst" "" } } } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}