all_01.tan.qmsg

eda 开发数字钟的设计具体编程代码和开发流程与设计图

{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK20M " "Info: No valid register-to-register data paths exist for clock \"CLK20M\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "KEY\[11\] register hhmmss:inst8\|si_mm\[2\] register hhmmss:inst8\|si_mm\[2\] 202.39 MHz 4.941 ns Internal " "Info: Clock \"KEY\[11\]\" has Internal fmax of 202.39 MHz between source register \"hhmmss:inst8\|si_mm\[2\]\" and destination register \"hhmmss:inst8\|si_mm\[2\]\" (period= 4.941 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.680 ns + Longest register register " "Info: + Longest register to register delay is 4.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hhmmss:inst8\|si_mm\[2\] 1 REG LC_X22_Y9_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y9_N9; Fanout = 5; REG Node = 'hhmmss:inst8\|si_mm\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hhmmss:inst8|si_mm[2] } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.442 ns) 1.716 ns hhmmss:inst8\|Equal1~65 2 COMB LC_X22_Y11_N8 1 " "Info: 2: + IC(1.274 ns) + CELL(0.442 ns) = 1.716 ns; Loc. = LC_X22_Y11_N8; Fanout = 1; COMB Node = 'hhmmss:inst8\|Equal1~65'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.716 ns" { hhmmss:inst8|si_mm[2] hhmmss:inst8|Equal1~65 } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.114 ns) 2.519 ns hhmmss:inst8\|Equal1~66 3 COMB LC_X21_Y11_N0 16 " "Info: 3: + IC(0.689 ns) + CELL(0.114 ns) = 2.519 ns; Loc. = LC_X21_Y11_N0; Fanout = 16; COMB Node = 'hhmmss:inst8\|Equal1~66'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.803 ns" { hhmmss:inst8|Equal1~65 hhmmss:inst8|Equal1~66 } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 86 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.478 ns) 4.680 ns hhmmss:inst8\|si_mm\[2\] 4 REG LC_X22_Y9_N9 5 " "Info: 4: + IC(1.683 ns) + CELL(0.478 ns) = 4.680 ns; Loc. = LC_X22_Y9_N9; Fanout = 5; REG Node = 'hhmmss:inst8\|si_mm\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.161 ns" { hhmmss:inst8|Equal1~66 hhmmss:inst8|si_mm[2] } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.034 ns ( 22.09 % ) " "Info: Total cell delay = 1.034 ns ( 22.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.646 ns ( 77.91 % ) " "Info: Total interconnect delay = 3.646 ns ( 77.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.680 ns" { hhmmss:inst8|si_mm[2] hhmmss:inst8|Equal1~65 hhmmss:inst8|Equal1~66 hhmmss:inst8|si_mm[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.680 ns" { hhmmss:inst8|si_mm[2] hhmmss:inst8|Equal1~65 hhmmss:inst8|Equal1~66 hhmmss:inst8|si_mm[2] } { 0.000ns 1.274ns 0.689ns 1.683ns } { 0.000ns 0.442ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT