📄 all_01.tan.qmsg
字号:
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk0 register hhmmss:inst8\|ss\[2\] register debugled:10\|temp_seg\[0\] 5.841 ns " "Info: Slack time is 5.841 ns for clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk0\" between source register \"hhmmss:inst8\|ss\[2\]\" and destination register \"debugled:10\|temp_seg\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "33.35 MHz 29.984 ns " "Info: Fmax is 33.35 MHz (period= 29.984 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "14.442 ns + Largest register register " "Info: + Largest register to register requirement is 14.442 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.833 ns + " "Info: + Setup relationship between source and destination is 20.833 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 19.000 ns " "Info: + Latch edge is 19.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CYC_PLL:inst\|altpll:altpll_component\|_clk0 41.666 ns 19.000 ns inverted 50 " "Info: Clock period of Destination clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with inverted offset of 19.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CYC_PLL:inst\|altpll:altpll_component\|_clk0 41.666 ns -1.833 ns 50 " "Info: Clock period of Source clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk0\" is 41.666 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.130 ns + Largest " "Info: + Largest clock skew is -6.130 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk0 destination 14.873 ns + Shortest register " "Info: + Shortest clock path from clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk0\" to destination register is 14.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CYC_PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 10; CLK Node = 'CYC_PLL:inst\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CYC_PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.935 ns) 2.542 ns clockall:9\|clock150:29\|clkout 2 REG LC_X24_Y6_N2 1 " "Info: 2: + IC(1.607 ns) + CELL(0.935 ns) = 2.542 ns; Loc. = LC_X24_Y6_N2; Fanout = 1; REG Node = 'clockall:9\|clock150:29\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.542 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout } "NODE_NAME" } } { "CLOCK150.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK150.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.935 ns) 4.032 ns clockall:9\|14 3 REG LC_X24_Y6_N0 2 " "Info: 3: + IC(0.555 ns) + CELL(0.935 ns) = 4.032 ns; Loc. = LC_X24_Y6_N0; Fanout = 2; REG Node = 'clockall:9\|14'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.490 ns" { clockall:9|clock150:29|clkout clockall:9|14 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 168 192 256 248 "14" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.935 ns) 5.742 ns clockall:9\|16 4 REG LC_X25_Y6_N2 2 " "Info: 4: + IC(0.775 ns) + CELL(0.935 ns) = 5.742 ns; Loc. = LC_X25_Y6_N2; Fanout = 2; REG Node = 'clockall:9\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.710 ns" { clockall:9|14 clockall:9|16 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 152 488 552 232 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 7.244 ns clockall:9\|18 5 REG LC_X25_Y6_N0 2 " "Info: 5: + IC(0.567 ns) + CELL(0.935 ns) = 7.244 ns; Loc. = LC_X25_Y6_N0; Fanout = 2; REG Node = 'clockall:9\|18'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.502 ns" { clockall:9|16 clockall:9|18 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 304 160 224 384 "18" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.935 ns) 8.954 ns clockall:9\|20 6 REG LC_X26_Y6_N2 2 " "Info: 6: + IC(0.775 ns) + CELL(0.935 ns) = 8.954 ns; Loc. = LC_X26_Y6_N2; Fanout = 2; REG Node = 'clockall:9\|20'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.710 ns" { clockall:9|18 clockall:9|20 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 288 376 440 368 "20" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 10.456 ns clockall:9\|24 7 REG LC_X26_Y6_N4 29 " "Info: 7: + IC(0.567 ns) + CELL(0.935 ns) = 10.456 ns; Loc. = LC_X26_Y6_N4; Fanout = 29; REG Node = 'clockall:9\|24'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.502 ns" { clockall:9|20 clockall:9|24 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 272 632 696 352 "24" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.711 ns) 14.873 ns debugled:10\|temp_seg\[0\] 8 REG LC_X20_Y7_N0 7 " "Info: 8: + IC(3.706 ns) + CELL(0.711 ns) = 14.873 ns; Loc. = LC_X20_Y7_N0; Fanout = 7; REG Node = 'debugled:10\|temp_seg\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.417 ns" { clockall:9|24 debugled:10|temp_seg[0] } "NODE_NAME" } } { "DEBUGLED.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.321 ns ( 42.50 % ) " "Info: Total cell delay = 6.321 ns ( 42.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.552 ns ( 57.50 % ) " "Info: Total interconnect delay = 8.552 ns ( 57.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.706ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk0 source 21.003 ns - Longest register " "Info: - Longest clock path from clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk0\" to source register is 21.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CYC_PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 10; CLK Node = 'CYC_PLL:inst\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CYC_PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.935 ns) 2.542 ns clockall:9\|clock150:29\|clkout 2 REG LC_X24_Y6_N2 1 " "Info: 2: + IC(1.607 ns) + CELL(0.935 ns) = 2.542 ns; Loc. = LC_X24_Y6_N2; Fanout = 1; REG Node = 'clockall:9\|clock150:29\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.542 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout } "NODE_NAME" } } { "CLOCK150.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK150.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.935 ns) 4.032 ns clockall:9\|14 3 REG LC_X24_Y6_N0 2 " "Info: 3: + IC(0.555 ns) + CELL(0.935 ns) = 4.032 ns; Loc. = LC_X24_Y6_N0; Fanout = 2; REG Node = 'clockall:9\|14'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.490 ns" { clockall:9|clock150:29|clkout clockall:9|14 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 168 192 256 248 "14" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.935 ns) 5.742 ns clockall:9\|16 4 REG LC_X25_Y6_N2 2 " "Info: 4: + IC(0.775 ns) + CELL(0.935 ns) = 5.742 ns; Loc. = LC_X25_Y6_N2; Fanout = 2; REG Node = 'clockall:9\|16'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.710 ns" { clockall:9|14 clockall:9|16 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 152 488 552 232 "16" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 7.244 ns clockall:9\|18 5 REG LC_X25_Y6_N0 2 " "Info: 5: + IC(0.567 ns) + CELL(0.935 ns) = 7.244 ns; Loc. = LC_X25_Y6_N0; Fanout = 2; REG Node = 'clockall:9\|18'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.502 ns" { clockall:9|16 clockall:9|18 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 304 160 224 384 "18" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.935 ns) 8.954 ns clockall:9\|20 6 REG LC_X26_Y6_N2 2 " "Info: 6: + IC(0.775 ns) + CELL(0.935 ns) = 8.954 ns; Loc. = LC_X26_Y6_N2; Fanout = 2; REG Node = 'clockall:9\|20'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.710 ns" { clockall:9|18 clockall:9|20 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 288 376 440 368 "20" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.935 ns) 10.456 ns clockall:9\|24 7 REG LC_X26_Y6_N4 29 " "Info: 7: + IC(0.567 ns) + CELL(0.935 ns) = 10.456 ns; Loc. = LC_X26_Y6_N4; Fanout = 29; REG Node = 'clockall:9\|24'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.502 ns" { clockall:9|20 clockall:9|24 } "NODE_NAME" } } { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 272 632 696 352 "24" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.663 ns) + CELL(0.935 ns) 15.054 ns clock2500:14\|clkout 8 REG LC_X9_Y6_N8 1 " "Info: 8: + IC(3.663 ns) + CELL(0.935 ns) = 15.054 ns; Loc. = LC_X9_Y6_N8; Fanout = 1; REG Node = 'clock2500:14\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.598 ns" { clockall:9|24 clock2500:14|clkout } "NODE_NAME" } } { "CLOCK2500.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2500.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.935 ns) 16.793 ns clock2:15\|clkout 9 REG LC_X8_Y6_N4 42 " "Info: 9: + IC(0.804 ns) + CELL(0.935 ns) = 16.793 ns; Loc. = LC_X8_Y6_N4; Fanout = 42; REG Node = 'clock2:15\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.739 ns" { clock2500:14|clkout clock2:15|clkout } "NODE_NAME" } } { "CLOCK2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 21.003 ns hhmmss:inst8\|ss\[2\] 10 REG LC_X18_Y7_N4 18 " "Info: 10: + IC(3.499 ns) + CELL(0.711 ns) = 21.003 ns; Loc. = LC_X18_Y7_N4; Fanout = 18; REG Node = 'hhmmss:inst8\|ss\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.210 ns" { clock2:15|clkout hhmmss:inst8|ss[2] } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.191 ns ( 39.00 % ) " "Info: Total cell delay = 8.191 ns ( 39.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.812 ns ( 61.00 % ) " "Info: Total interconnect delay = 12.812 ns ( 61.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.663ns 0.804ns 3.499ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.706ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.663ns 0.804ns 3.499ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "DEBUGLED.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd" 86 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.706ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.663ns 0.804ns 3.499ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.601 ns - Longest register register " "Info: - Longest register to register delay is 8.601 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hhmmss:inst8\|ss\[2\] 1 REG LC_X18_Y7_N4 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y7_N4; Fanout = 18; REG Node = 'hhmmss:inst8\|ss\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hhmmss:inst8|ss[2] } "NODE_NAME" } } { "hhmmss.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/hhmmss.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.175 ns) + CELL(0.442 ns) 1.617 ns HEX2DEC:inst6\|LessThan2~97 2 COMB LC_X18_Y7_N0 5 " "Info: 2: + IC(1.175 ns) + CELL(0.442 ns) = 1.617 ns; Loc. = LC_X18_Y7_N0; Fanout = 5; COMB Node = 'HEX2DEC:inst6\|LessThan2~97'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.617 ns" { hhmmss:inst8|ss[2] HEX2DEC:inst6|LessThan2~97 } "NODE_NAME" } } { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.209 ns) + CELL(0.114 ns) 2.940 ns HEX2DEC:inst6\|LessThan5~130 3 COMB LC_X16_Y7_N3 5 " "Info: 3: + IC(1.209 ns) + CELL(0.114 ns) = 2.940 ns; Loc. = LC_X16_Y7_N3; Fanout = 5; COMB Node = 'HEX2DEC:inst6\|LessThan5~130'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.323 ns" { HEX2DEC:inst6|LessThan2~97 HEX2DEC:inst6|LessThan5~130 } "NODE_NAME" } } { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 29 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.151 ns) + CELL(0.292 ns) 4.383 ns HEX2DEC:inst6\|Add0~3968 4 COMB LC_X17_Y7_N0 1 " "Info: 4: + IC(1.151 ns) + CELL(0.292 ns) = 4.383 ns; Loc. = LC_X17_Y7_N0; Fanout = 1; COMB Node = 'HEX2DEC:inst6\|Add0~3968'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.443 ns" { HEX2DEC:inst6|LessThan5~130 HEX2DEC:inst6|Add0~3968 } "NODE_NAME" } } { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.114 ns) 5.612 ns HEX2DEC:inst6\|Add0~3970 5 COMB LC_X20_Y7_N2 1 " "Info: 5: + IC(1.115 ns) + CELL(0.114 ns) = 5.612 ns; Loc. = LC_X20_Y7_N2; Fanout = 1; COMB Node = 'HEX2DEC:inst6\|Add0~3970'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.229 ns" { HEX2DEC:inst6|Add0~3968 HEX2DEC:inst6|Add0~3970 } "NODE_NAME" } } { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.590 ns) 6.636 ns HEX2DEC:inst6\|Add0~3977 6 COMB LC_X20_Y7_N6 1 " "Info: 6: + IC(0.434 ns) + CELL(0.590 ns) = 6.636 ns; Loc. = LC_X20_Y7_N6; Fanout = 1; COMB Node = 'HEX2DEC:inst6\|Add0~3977'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.024 ns" { HEX2DEC:inst6|Add0~3970 HEX2DEC:inst6|Add0~3977 } "NODE_NAME" } } { "HEX2DEC.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/HEX2DEC.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 6.932 ns debugled:10\|Mux16~1398 7 COMB LC_X20_Y7_N7 1 " "Info: 7: + IC(0.182 ns) + CELL(0.114 ns) = 6.932 ns; Loc. = LC_X20_Y7_N7; Fanout = 1; COMB Node = 'debugled:10\|Mux16~1398'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { HEX2DEC:inst6|Add0~3977 debugled:10|Mux16~1398 } "NODE_NAME" } } { "DEBUGLED.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 7.672 ns debugled:10\|Mux16~1399 8 COMB LC_X20_Y7_N9 1 " "Info: 8: + IC(0.448 ns) + CELL(0.292 ns) = 7.672 ns; Loc. = LC_X20_Y7_N9; Fanout = 1; COMB Node = 'debugled:10\|Mux16~1399'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.740 ns" { debugled:10|Mux16~1398 debugled:10|Mux16~1399 } "NODE_NAME" } } { "DEBUGLED.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.478 ns) 8.601 ns debugled:10\|temp_seg\[0\] 9 REG LC_X20_Y7_N0 7 " "Info: 9: + IC(0.451 ns) + CELL(0.478 ns) = 8.601 ns; Loc. = LC_X20_Y7_N0; Fanout = 7; REG Node = 'debugled:10\|temp_seg\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.929 ns" { debugled:10|Mux16~1399 debugled:10|temp_seg[0] } "NODE_NAME" } } { "DEBUGLED.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/DEBUGLED.vhd" 86 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.436 ns ( 28.32 % ) " "Info: Total cell delay = 2.436 ns ( 28.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.165 ns ( 71.68 % ) " "Info: Total interconnect delay = 6.165 ns ( 71.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.601 ns" { hhmmss:inst8|ss[2] HEX2DEC:inst6|LessThan2~97 HEX2DEC:inst6|LessThan5~130 HEX2DEC:inst6|Add0~3968 HEX2DEC:inst6|Add0~3970 HEX2DEC:inst6|Add0~3977 debugled:10|Mux16~1398 debugled:10|Mux16~1399 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.601 ns" { hhmmss:inst8|ss[2] HEX2DEC:inst6|LessThan2~97 HEX2DEC:inst6|LessThan5~130 HEX2DEC:inst6|Add0~3968 HEX2DEC:inst6|Add0~3970 HEX2DEC:inst6|Add0~3977 debugled:10|Mux16~1398 debugled:10|Mux16~1399 debugled:10|temp_seg[0] } { 0.000ns 1.175ns 1.209ns 1.151ns 1.115ns 0.434ns 0.182ns 0.448ns 0.451ns } { 0.000ns 0.442ns 0.114ns 0.292ns 0.114ns 0.590ns 0.114ns 0.292ns 0.478ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.873 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 debugled:10|temp_seg[0] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.706ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "21.003 ns" { CYC_PLL:inst|altpll:altpll_component|_clk0 clockall:9|clock150:29|clkout clockall:9|14 clockall:9|16 clockall:9|18 clockall:9|20 clockall:9|24 clock2500:14|clkout clock2:15|clkout hhmmss:inst8|ss[2] } { 0.000ns 1.607ns 0.555ns 0.775ns 0.567ns 0.775ns 0.567ns 3.663ns 0.804ns 3.499ns } { 0.000ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.601 ns" { hhmmss:inst8|ss[2] HEX2DEC:inst6|LessThan2~97 HEX2DEC:inst6|LessThan5~130 HEX2DEC:inst6|Add0~3968 HEX2DEC:inst6|Add0~3970 HEX2DEC:inst6|Add0~3977 debugled:10|Mux16~1398 debugled:10|Mux16~1399 debugled:10|temp_seg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.601 ns" { hhmmss:inst8|ss[2] HEX2DEC:inst6|LessThan2~97 HEX2DEC:inst6|LessThan5~130 HEX2DEC:inst6|Add0~3968 HEX2DEC:inst6|Add0~3970 HEX2DEC:inst6|Add0~3977 debugled:10|Mux16~1398 debugled:10|Mux16~1399 debugled:10|temp_seg[0] } { 0.000ns 1.175ns 1.209ns 1.151ns 1.115ns 0.434ns 0.182ns 0.448ns 0.451ns } { 0.000ns 0.442ns 0.114ns 0.292ns 0.114ns 0.590ns 0.114ns 0.292ns 0.478ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk1 register clock_spk:17\|count\[6\] register clock_spk:17\|clkout 6.33 ns " "Info: Slack time is 6.33 ns for clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk1\" between source register \"clock_spk:17\|count\[6\]\" and destination register \"clock_spk:17\|clkout\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "96.75 MHz 10.336 ns " "Info: Fmax is 96.75 MHz (period= 10.336 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "16.405 ns + Largest register register " "Info: + Largest register to register requirement is 16.405 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "16.666 ns + " "Info: + Setup relationship between source and destination is 16.666 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 14.833 ns " "Info: + Latch edge is 14.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CYC_PLL:inst\|altpll:altpll_component\|_clk1 16.666 ns -1.833 ns 50 " "Info: Clock period of Destination clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk1\" is 16.666 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CYC_PLL:inst\|altpll:altpll_component\|_clk1 16.666 ns -1.833 ns 50 " "Info: Clock period of Source clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk1\" is 16.666 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk1 destination 6.672 ns + Shortest register " "Info: + Shortest clock path from clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk1\" to destination register is 6.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CYC_PLL:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 7; CLK Node = 'CYC_PLL:inst\|altpll:altpll_component\|_clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CYC_PLL:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.565 ns) + CELL(0.935 ns) 2.500 ns clock40:inst3\|clkout 2 REG LC_X8_Y6_N2 13 " "Info: 2: + IC(1.565 ns) + CELL(0.935 ns) = 2.500 ns; Loc. = LC_X8_Y6_N2; Fanout = 13; REG Node = 'clock40:inst3\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout } "NODE_NAME" } } { "CLOCK40.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.461 ns) + CELL(0.711 ns) 6.672 ns clock_spk:17\|clkout 3 REG LC_X18_Y2_N7 8 " "Info: 3: + IC(3.461 ns) + CELL(0.711 ns) = 6.672 ns; Loc. = LC_X18_Y2_N7; Fanout = 8; REG Node = 'clock_spk:17\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.172 ns" { clock40:inst3|clkout clock_spk:17|clkout } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 24.67 % ) " "Info: Total cell delay = 1.646 ns ( 24.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.026 ns ( 75.33 % ) " "Info: Total interconnect delay = 5.026 ns ( 75.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CYC_PLL:inst\|altpll:altpll_component\|_clk1 source 6.672 ns - Longest register " "Info: - Longest clock path from clock \"CYC_PLL:inst\|altpll:altpll_component\|_clk1\" to source register is 6.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CYC_PLL:inst\|altpll:altpll_component\|_clk1 1 CLK PLL_1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 7; CLK Node = 'CYC_PLL:inst\|altpll:altpll_component\|_clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CYC_PLL:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.565 ns) + CELL(0.935 ns) 2.500 ns clock40:inst3\|clkout 2 REG LC_X8_Y6_N2 13 " "Info: 2: + IC(1.565 ns) + CELL(0.935 ns) = 2.500 ns; Loc. = LC_X8_Y6_N2; Fanout = 13; REG Node = 'clock40:inst3\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout } "NODE_NAME" } } { "CLOCK40.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.461 ns) + CELL(0.711 ns) 6.672 ns clock_spk:17\|count\[6\] 3 REG LC_X21_Y3_N7 15 " "Info: 3: + IC(3.461 ns) + CELL(0.711 ns) = 6.672 ns; Loc. = LC_X21_Y3_N7; Fanout = 15; REG Node = 'clock_spk:17\|count\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.172 ns" { clock40:inst3|clkout clock_spk:17|count[6] } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 24.67 % ) " "Info: Total cell delay = 1.646 ns ( 24.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.026 ns ( 75.33 % ) " "Info: Total interconnect delay = 5.026 ns ( 75.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 20 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 11 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.075 ns - Longest register register " "Info: - Longest register to register delay is 10.075 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock_spk:17\|count\[6\] 1 REG LC_X21_Y3_N7 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y3_N7; Fanout = 15; REG Node = 'clock_spk:17\|count\[6\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock_spk:17|count[6] } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.670 ns) + CELL(0.590 ns) 2.260 ns clock_spk:17\|Equal2~74 2 COMB LC_X20_Y5_N7 2 " "Info: 2: + IC(1.670 ns) + CELL(0.590 ns) = 2.260 ns; Loc. = LC_X20_Y5_N7; Fanout = 2; COMB Node = 'clock_spk:17\|Equal2~74'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.260 ns" { clock_spk:17|count[6] clock_spk:17|Equal2~74 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.590 ns) 3.279 ns clock_spk:17\|Equal6~88 3 COMB LC_X20_Y5_N4 14 " "Info: 3: + IC(0.429 ns) + CELL(0.590 ns) = 3.279 ns; Loc. = LC_X20_Y5_N4; Fanout = 14; COMB Node = 'clock_spk:17\|Equal6~88'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.019 ns" { clock_spk:17|Equal2~74 clock_spk:17|Equal6~88 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 88 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.442 ns) 4.942 ns clock_spk:17\|LessThan4~110 4 COMB LC_X20_Y4_N0 13 " "Info: 4: + IC(1.221 ns) + CELL(0.442 ns) = 4.942 ns; Loc. = LC_X20_Y4_N0; Fanout = 13; COMB Node = 'clock_spk:17\|LessThan4~110'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.663 ns" { clock_spk:17|Equal6~88 clock_spk:17|LessThan4~110 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.292 ns) 6.513 ns clock_spk:17\|Mux0~3596 5 COMB LC_X19_Y2_N2 1 " "Info: 5: + IC(1.279 ns) + CELL(0.292 ns) = 6.513 ns; Loc. = LC_X19_Y2_N2; Fanout = 1; COMB Node = 'clock_spk:17\|Mux0~3596'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.571 ns" { clock_spk:17|LessThan4~110 clock_spk:17|Mux0~3596 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.292 ns) 7.541 ns clock_spk:17\|Mux0~3597 6 COMB LC_X18_Y2_N9 1 " "Info: 6: + IC(0.736 ns) + CELL(0.292 ns) = 7.541 ns; Loc. = LC_X18_Y2_N9; Fanout = 1; COMB Node = 'clock_spk:17\|Mux0~3597'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.028 ns" { clock_spk:17|Mux0~3596 clock_spk:17|Mux0~3597 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.464 ns) + CELL(0.292 ns) 8.297 ns clock_spk:17\|Mux0~3620 7 COMB LC_X18_Y2_N0 1 " "Info: 7: + IC(0.464 ns) + CELL(0.292 ns) = 8.297 ns; Loc. = LC_X18_Y2_N0; Fanout = 1; COMB Node = 'clock_spk:17\|Mux0~3620'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.756 ns" { clock_spk:17|Mux0~3597 clock_spk:17|Mux0~3620 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.593 ns clock_spk:17\|Mux0~3621 8 COMB LC_X18_Y2_N1 1 " "Info: 8: + IC(0.182 ns) + CELL(0.114 ns) = 8.593 ns; Loc. = LC_X18_Y2_N1; Fanout = 1; COMB Node = 'clock_spk:17\|Mux0~3621'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { clock_spk:17|Mux0~3620 clock_spk:17|Mux0~3621 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.889 ns clock_spk:17\|Mux0~3603 9 COMB LC_X18_Y2_N2 1 " "Info: 9: + IC(0.182 ns) + CELL(0.114 ns) = 8.889 ns; Loc. = LC_X18_Y2_N2; Fanout = 1; COMB Node = 'clock_spk:17\|Mux0~3603'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { clock_spk:17|Mux0~3621 clock_spk:17|Mux0~3603 } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.738 ns) 10.075 ns clock_spk:17\|clkout 10 REG LC_X18_Y2_N7 8 " "Info: 10: + IC(0.448 ns) + CELL(0.738 ns) = 10.075 ns; Loc. = LC_X18_Y2_N7; Fanout = 8; REG Node = 'clock_spk:17\|clkout'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.186 ns" { clock_spk:17|Mux0~3603 clock_spk:17|clkout } "NODE_NAME" } } { "CLOCK_SPK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK_SPK.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.464 ns ( 34.38 % ) " "Info: Total cell delay = 3.464 ns ( 34.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.611 ns ( 65.62 % ) " "Info: Total interconnect delay = 6.611 ns ( 65.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.075 ns" { clock_spk:17|count[6] clock_spk:17|Equal2~74 clock_spk:17|Equal6~88 clock_spk:17|LessThan4~110 clock_spk:17|Mux0~3596 clock_spk:17|Mux0~3597 clock_spk:17|Mux0~3620 clock_spk:17|Mux0~3621 clock_spk:17|Mux0~3603 clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.075 ns" { clock_spk:17|count[6] clock_spk:17|Equal2~74 clock_spk:17|Equal6~88 clock_spk:17|LessThan4~110 clock_spk:17|Mux0~3596 clock_spk:17|Mux0~3597 clock_spk:17|Mux0~3620 clock_spk:17|Mux0~3621 clock_spk:17|Mux0~3603 clock_spk:17|clkout } { 0.000ns 1.670ns 0.429ns 1.221ns 1.279ns 0.736ns 0.464ns 0.182ns 0.182ns 0.448ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.292ns 0.292ns 0.292ns 0.114ns 0.114ns 0.738ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|clkout } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.672 ns" { CYC_PLL:inst|altpll:altpll_component|_clk1 clock40:inst3|clkout clock_spk:17|count[6] } { 0.000ns 1.565ns 3.461ns } { 0.000ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.075 ns" { clock_spk:17|count[6] clock_spk:17|Equal2~74 clock_spk:17|Equal6~88 clock_spk:17|LessThan4~110 clock_spk:17|Mux0~3596 clock_spk:17|Mux0~3597 clock_spk:17|Mux0~3620 clock_spk:17|Mux0~3621 clock_spk:17|Mux0~3603 clock_spk:17|clkout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.075 ns" { clock_spk:17|count[6] clock_spk:17|Equal2~74 clock_spk:17|Equal6~88 clock_spk:17|LessThan4~110 clock_spk:17|Mux0~3596 clock_spk:17|Mux0~3597 clock_spk:17|Mux0~3620 clock_spk:17|Mux0~3621 clock_spk:17|Mux0~3603 clock_spk:17|clkout } { 0.000ns 1.670ns 0.429ns 1.221ns 1.279ns 0.736ns 0.464ns 0.182ns 0.182ns 0.448ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.292ns 0.292ns 0.292ns 0.114ns 0.114ns 0.738ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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