all_01.tan.qmsg

eda 开发数字钟的设计具体编程代码和开发流程与设计图

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "KEY\[11\] " "Info: Assuming node \"KEY\[11\]\" is an undefined clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[11\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "KEY\[10\] " "Info: Assuming node \"KEY\[10\]\" is an undefined clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[10\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "KEY\[12\] " "Info: Assuming node \"KEY\[12\]\" is an undefined clock" {  } { { "all_01.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/all_01.bdf" { { 632 224 392 648 "KEY\[12..1\]" "" } { 600 704 792 616 "KEY\[7..1\]" "" } { 208 192 243 224 "KEY\[12\]" "" } { 224 192 243 240 "KEY\[11\]" "" } { 240 192 243 256 "KEY\[10\]" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KEY\[12\]" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|clock150:29\|clkout " "Info: Detected ripple clock \"clockall:9\|clock150:29\|clkout\" as buffer" {  } { { "CLOCK150.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK150.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|clock150:29\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|14 " "Info: Detected ripple clock \"clockall:9\|14\" as buffer" {  } { { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 168 192 256 248 "14" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|14" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|16 " "Info: Detected ripple clock \"clockall:9\|16\" as buffer" {  } { { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 152 488 552 232 "16" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|16" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|18 " "Info: Detected ripple clock \"clockall:9\|18\" as buffer" {  } { { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 304 160 224 384 "18" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|18" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock2500:14\|clkout " "Info: Detected ripple clock \"clock2500:14\|clkout\" as buffer" {  } { { "CLOCK2500.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2500.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock2500:14\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|20 " "Info: Detected ripple clock \"clockall:9\|20\" as buffer" {  } { { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 288 376 440 368 "20" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|20" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clockall:9\|24 " "Info: Detected ripple clock \"clockall:9\|24\" as buffer" {  } { { "clockall.gdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/clockall.gdf" { { 272 632 696 352 "24" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clockall:9\|24" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock2:15\|clkout " "Info: Detected ripple clock \"clock2:15\|clkout\" as buffer" {  } { { "CLOCK2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK2.vhd" 15 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock2:15\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clock40:inst3\|clkout " "Info: Detected ripple clock \"clock40:inst3\|clkout\" as buffer" {  } { { "CLOCK40.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/quar42_CYC_DEMO_V2_test/CLOCK40.vhd" 13 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clock40:inst3\|clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}