all_01.tan.rpt

eda 开发数字钟的设计具体编程代码和开发流程与设计图

; Clock Setup: 'CYC_PLL:inst|altpll:altpll_component|_clk0' ; 5.841 ns ; 24.00 MHz ( period = 41.666 ns ) ; 33.35 MHz ( period = 29.984 ns ) ; hhmmss:inst8|ss[2]     ; debugled:10|temp_seg[0] ; CYC_PLL:inst|altpll:altpll_component|_clk0 ; CYC_PLL:inst|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CYC_PLL:inst|altpll:altpll_component|_clk1' ; 6.330 ns ; 60.00 MHz ( period = 16.666 ns ) ; 96.75 MHz ( period = 10.336 ns ) ; clock_spk:17|count[6]  ; clock_spk:17|clkout     ; CYC_PLL:inst|altpll:altpll_component|_clk1 ; CYC_PLL:inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'KEY[11]'                                    ; N/A      ; None                             ; 202.39 MHz ( period = 4.941 ns ) ; hhmmss:inst8|si_mm[2]  ; hhmmss:inst8|si_mm[2]   ; KEY[11]                                    ; KEY[11]                                    ; 0            ;
; Clock Setup: 'KEY[10]'                                    ; N/A      ; None                             ; 214.22 MHz ( period = 4.668 ns ) ; hhmmss:inst8|si_ss[4]  ; hhmmss:inst8|si_ss[4]   ; KEY[10]                                    ; KEY[10]                                    ; 0            ;
; Clock Setup: 'KEY[12]'                                    ; N/A      ; None                             ; 229.78 MHz ( period = 4.352 ns ) ; hhmmss:inst8|si_hh[5]  ; hhmmss:inst8|si_hh[7]   ; KEY[12]                                    ; KEY[12]                                    ; 0            ;
; Clock Hold: 'CYC_PLL:inst|altpll:altpll_component|_clk1'  ; 0.822 ns ; 60.00 MHz ( period = 16.666 ns ) ; N/A                              ; clock40:inst3|count[5] ; clock40:inst3|count[5]  ; CYC_PLL:inst|altpll:altpll_component|_clk1 ; CYC_PLL:inst|altpll:altpll_component|_clk1 ; 0            ;
; Clock Hold: 'CYC_PLL:inst|altpll:altpll_component|_clk0'  ; 1.031 ns ; 24.00 MHz ( period = 41.666 ns ) ; N/A                              ; clockall:9|14          ; clockall:9|14           ; CYC_PLL:inst|altpll:altpll_component|_clk0 ; CYC_PLL:inst|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                              ;          ;                                  ;                                  ;                        ;                         ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+----------+----------------------------------+----------------------------------+------------------------+-------------------------+--------------------------------------------+--------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Minimum tpd to report                                 ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; CYC_PLL:inst|altpll:altpll_component|_clk0 ;                    ; PLL output ; 24.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK20M   ; 6                     ; 5                   ; -1.833 ns ;              ;
; CYC_PLL:inst|altpll:altpll_component|_clk1 ;                    ; PLL output ; 60.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK20M   ; 3                     ; 1                   ; -1.833 ns ;              ;
; CLK20M                                     ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; KEY[11]                                    ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; KEY[10]                                    ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; KEY[12]                                    ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+