📄 wunios.ptf
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SYSTEM wuNIOS
{
System_Wizard_Version = "4.10";
System_Wizard_Build = "181";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
board_class = "";
hdl_language = "vhdl";
view_master_columns = "0";
view_master_priorities = "0";
device_family_id = "CYCLONE";
name_column_width = "300";
desc_column_width = "300";
bustype_column_width = "0";
base_column_width = "75";
end_column_width = "75";
view_frame_window = "maximized";
}
MODULE cpu_0
{
class = "altera_nios2";
class_version = "1.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
MASTER instruction_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
# This is only for hbreak test bench, not for human consumption
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
}
}
MASTER data_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Data_Master = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
# only self-component-mastered
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x00000000";
Is_Memory_Device = "1";
# FIXME. Needed for now.
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
# JTAG_Hub_Base_ID is :
# ((0x0) << 27) + # Node Ver
# ((0x22) << 19) + # Node ID
# ((0x46) << 8 ) # Mfg_ID
# = 0x11046 = 69702
JTAG_Hub_Base_Id = "69702";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
# Invokes Visual Stdio Perl debugger for cpu_core_select.pl
asp_debug = "0";
# Invokes Visual Stdio Perl debugger for cpu_core.pl
# This is normally what you want.
asp_core_debug = "0";
CPU_Architecture = "nios2";
# CONSTANT CONSTANT
# User Settings
do_generate = "1";
# ALWAYS GENERATE WHEN ASKED
cpu_selection = "s";
# {e, s, f, turbo} (used by GUI)
CPU_Implementation = "small";
# {tiny, small, fast, turbo}
cache_has_dcache = "0";
# {0, 1}
cache_has_icache = "1";
# {0, 1}
cache_dcache_size = "2048";
# {512, 1024, 2048, ... 65536}
cache_icache_size = "4096";
# {512, 1024, 2048, ... 65536}
include_debug = "0";
# LEAVE AS 0 (pre-OCI debug solution)
include_trace = "0";
# ALWAYS SET TO 0 (pre-OCI trace solution)
include_oci = "1";
# {0, 1}
debug_level = "2";
# {1, 2, 3, 4, 5} (used by GUI)
oci_offchip_trace = "0";
# {0, 1} Support off-chip trace signals (FS2 box required)
oci_onchip_trace = "0";
# {0, 1} Support On-chip trace memory
oci_data_trace = "0";
# {0, 1} Support data trace
oci_trace_addr_width = "7";
# {7 ... 16}
oci_num_xbrk = "0";
# {0, 1, 4} Number of instruction hw breakpoints
oci_num_dbrk = "0";
# {0, 2, 4} Number of data hw watchpoints
oci_dbrk_trace = "0";
# {0, 1} Enable watchpoints to trigger trace
oci_dbrk_pairs = "0";
# {0, 1} Enable watchpoints to work in pairs
oci_num_pm = "0";
# {0, 1, 2} Number of performance monitors
oci_pm_width = "40";
# {32..65} Number of bits in performance monitor counter
oci_debugreq_signals = "0";
# (Leave as 0 because no one seems to use it.)
hardware_multiply_present = "0";
# {0, 1}
remove_hardware_multiplier = "0";
# {0, 1}
hardware_divide_present = "0";
# {0, 1} (Forced to 0 if no multiplier present.)
# User setting for now, to let folks determine the best values.
bht_ptr_sz = "8";
# {8, 9, 10, 11}
# $OCI_SBI/Is_Enabled = {0, 1}
# Binding Page
reset_slave = "";
# Binding
reset_offset = "0x0";
# Binding
exc_slave = "";
# Binding
exc_offset = "0x100";
# Binding
break_slave = "cpu_0/jtag_debug_module";
# Binding
break_offset = "0x00000020";
# Binding # FIXME make 0x20
break_slave_override = "";
# Binding
break_offset_override = "0x20";
# Binding
legacy_sdk_support = "0";
# Binding
# This flag is set manually in the system PTF file
# to enable features related to Altera internal testing.
altera_internal_test = "0";
# Altera Internal Test Settings
full_waveform_signals = "0";
# {0, 1}
activate_model_checker = "0";
# {0, 1}
activate_trace = "1";
# {0, 1}
activate_monitors = "1";
# {0, 1}
activate_test_end_checker = "0";
# {0, 1}
bit_31_bypass_dcache = "1";
# {0, 1}
always_bypass_dcache = "0";
# {0, 1}
always_encrypt = "1";
# {0, 1}
hdl_sim_caches_cleared = "1";
# {0, 1}
clear_x_bits_ld_non_bypass = "1";
# {0, 1}
# Allow the full address range to be used
allow_full_address_range = "0";
# {0, 1}
# Altera Internal Test Settings -- Architecture Tuning
consistent_synthesis = "0";
# {0, 1}
ibuf_ptr_sz = "4";
# {2, 3, 4, 5}
jtb_ptr_sz = "5";
# {5, 6, 7, 8}
performance_counters_present = "0";
# {0, 1}
performance_counters_width = "32";
# {16, 24, 32}
ras_ptr_sz = "4";
# {3, 4, 5}
# Altera Internal Test Settings -- Hierarchy Control
inst_decode_in_submodule = "0";
register_dependency_in_submodule = "0";
source_operands_in_submodule = "0";
alu_in_submodule = "0";
stdata_in_submodule = "0";
shift_rot_2N_in_submodule = "0";
control_regs_in_submodule = "0";
M_inst_result_mux_in_submodule = "0";
dcache_load_aligner_in_submodule = "0";
hardware_divide_in_submodule = "0";
mult_result_mux_in_submodule = "0";
shift_rotate_in_submodule = "0";
register_file_write_data_mux_in_submodule = "0";
avalon_imaster_in_submodule = "0";
avalon_dmaster_in_submodule = "0";
avalon_load_aligner_in_submodule = "0";
hbreak_test = "0";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
# Assignments associated with the flash and EPCS boot copiers.
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "0";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
mult_cell_in_submodule = "";
license_status = "";
germs_monitor_id = "02312";
mainmem_slave = "";
datamem_slave = "";
maincomm_slave = "";
debugcomm_slave = "";
}
SYSTEM_BUILDER_INFO
{
Parameters_Signature = "";
Is_CPU = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "STRATIX,STRATIXII,CYCLONE";
# Controls the prefix of the default instance name chosen
# by SOPC builder (it adds a unique numeric suffix).
Default_Module_Name = "cpu";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
Settings_Summary = "Nios II/s
<br> 4-Kbyte Instruction Cache
<br> JTAG Debug Module
";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "2.1";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
}
}
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