📄 all_01.qsf
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# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
# The default values for assignments are stored in the file
# all_01_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:21:45 APRIL 06, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name BDF_FILE all_01.bdf
set_global_assignment -name VHDL_FILE HEX2DEC.vhd
set_global_assignment -name VHDL_FILE CLOCK40.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_16 -to CLK20M
set_location_assignment PIN_4 -to EXA_IO1
set_location_assignment PIN_2 -to SPK
set_location_assignment PIN_124 -to EX_D[1]
set_location_assignment PIN_123 -to EX_D[2]
set_location_assignment PIN_122 -to EX_D[3]
set_location_assignment PIN_121 -to EX_D[4]
set_location_assignment PIN_120 -to EX_D[5]
set_location_assignment PIN_119 -to EX_D[6]
set_location_assignment PIN_114 -to EX_D[7]
set_location_assignment PIN_113 -to EX_D[8]
set_location_assignment PIN_112 -to EX_D[9]
set_location_assignment PIN_111 -to EX_D[10]
set_location_assignment PIN_110 -to EX_D[11]
set_location_assignment PIN_109 -to EX_D[12]
set_location_assignment PIN_126 -to DIG[1]
set_location_assignment PIN_125 -to DIG[2]
set_location_assignment PIN_128 -to DIG[3]
set_location_assignment PIN_127 -to DIG[4]
set_location_assignment PIN_130 -to DIG[5]
set_location_assignment PIN_129 -to DIG[6]
set_location_assignment PIN_142 -to SEG[1]
set_location_assignment PIN_141 -to SEG[2]
set_location_assignment PIN_140 -to SEG[3]
set_location_assignment PIN_139 -to SEG[4]
set_location_assignment PIN_134 -to SEG[5]
set_location_assignment PIN_133 -to SEG[6]
set_location_assignment PIN_132 -to SEG[7]
set_location_assignment PIN_131 -to SEG[8]
set_location_assignment PIN_59 -to KEY[1]
set_location_assignment PIN_60 -to KEY[2]
set_location_assignment PIN_61 -to KEY[3]
set_location_assignment PIN_62 -to KEY[4]
set_location_assignment PIN_67 -to KEY[5]
set_location_assignment PIN_68 -to KEY[6]
set_location_assignment PIN_69 -to KEY[7]
set_location_assignment PIN_70 -to KEY[8]
set_location_assignment PIN_71 -to KEY[9]
set_location_assignment PIN_72 -to KEY[10]
set_location_assignment PIN_73 -to KEY[11]
set_location_assignment PIN_74 -to KEY[12]
set_location_assignment PIN_1 -to WORKING_LED
set_location_assignment PIN_108 -to FP_DATA_DIR
# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY all_01
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS
# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name AUTO_RESTART_CONFIGURATION ON
# Simulator Assignments
# =====================
set_global_assignment -name START_TIME "0 ns"
set_global_assignment -name GLITCH_INTERVAL 0.0
set_global_assignment -name END_TIME 100
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP off
# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
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