hhmmss.vhd

eda 开发数字钟的设计具体编程代码和开发流程与设计图

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity hhmmss is
  port(set_hh:in std_logic;
       set_mm:in std_logic;
       set_ss:in std_logic;
       clkin:in std_logic;  --1HZ   
       hh   :out integer range 0 to 255;  
       mm   :out integer range 0 to 255;  
       ss   :out integer range 0 to 255  
       );
end entity;

architecture arc of hhmmss is
signal var_hh:integer range 0 to 255;
signal var_mm:integer range 0 to 255;
signal var_ss:integer range 0 to 255;
    begin

--set time
    process(set_ss)
    variable si_ss:integer range 0 to 255;
    begin
    if(set_ss'event and set_ss='0')then
    
     if (si_ss = 59) then
    		si_ss := 0;
          else 
         si_ss:=si_ss+1;
          
       end if;
     var_ss<=si_ss;
    end if;
  
  end process;
process(set_mm)
  variable si_mm:integer range 0 to 255; 
     begin
   
   if(set_mm'event and set_mm='0')then
    
     if (si_mm = 59) then
    		si_mm := 0;
          else 
         si_mm:=si_mm+1;
       
       end if;
     var_mm<=si_mm;
    end if;
    
  end process;
 process(set_hh)
    variable si_hh:integer range 0 to 255;
     begin
    
   if(set_hh'event and set_hh='0')then
    
     if (si_hh = 23) then
    		si_hh:= 0;
          else 
         si_hh:=si_hh+1;
         
       end if;
     var_hh<=si_hh;
    end if;
     
  end process;
--times
  process(clkin) 
  begin   
       if (clkin'event and clkin='1') then
       	if (var_ss = 59) then
    		var_ss<= 0;
    		if (var_mm = 59) then
    			var_mm<= 0;
    			if (var_hh = 23) then
    				var_hh<= 0;
    			else
    				var_hh<= var_hh + 1;
    			end if;
    		else
    			var_mm<= var_mm + 1;
    		end if;
    	else
    	   	var_ss<=var_ss+1;	    	
    	end if;
    hh<=var_hh;
     mm<=var_mm;
     ss<=var_ss;
    end if;
   end process;
end arc;