debugled.vhd

eda 开发数字钟的设计具体编程代码和开发流程与设计图

--*************************************************************************************--
--Colour Sort Machine/Test circurt/Debug_led board V2.0/2001.12.07
--EIST Department,Nankai University
--Debug part/debug/debugled
--Src file:debugled.vhd
--Serial number:019
--2001----2002
--*************************************************************************************--
--*************************************************************************************--
--use for led code
--EIST Department,Nankai University
-- 5 4      3 2      1 0   :--digit order
--din_l    din_m    din_r  :--seg order
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity debugled is
	port(din_l,din_m,din_r:in std_logic_vector(7 downto 0);
	     clk	:in std_logic;	--about 5kHz~~~10kHz
	     seg:	out std_logic_vector(7 downto 0);
	     digit:	out std_logic_vector(5 downto 0)
	     );
end debugled;
architecture arc of debugled is	     
signal temp_l_h,temp_l_l:std_logic_vector(3 downto 0); --5 4
signal temp_m_h,temp_m_l:std_logic_vector(3 downto 0); --3 2
signal temp_r_h,temp_r_l:std_logic_vector(3 downto 0); --1 0
signal temp_seg:std_logic_vector(3 downto 0);  --change every big clock 
signal segbuff:std_logic_vector(7 downto 0);
begin
--divide one 8-bit data to two 4-bit data
temp_l_l(3 downto 0)<=din_l(7 downto 4);--dig 5
temp_l_h(3 downto 0)<=din_l(3 downto 0);--dig 4
temp_m_l(3 downto 0)<=din_m(7 downto 4);--dig 3
temp_m_h(3 downto 0)<=din_m(3 downto 0);--dig 2
temp_r_l(3 downto 0)<=din_r(7 downto 4);--dig 1
temp_r_h(3 downto 0)<=din_r(3 downto 0);--dig 0
seg(7 downto 0)<=segbuff(7 downto 0);
--code
	process(temp_seg)
	begin
		case temp_seg is
				when "0000"=>
					segbuff<="00111111";--0
				when "0001"=>
					segbuff<="00000110";--1
				when "0010"=>
					segbuff<="01011011";--2
				when "0011"=>
					segbuff<="01001111";--3
				when "0100"=>
					segbuff<="01100110";--4
				when "0101"=>
					segbuff<="01101101";--5
				when "0110"=>
					segbuff<="01111101";--6
				when "0111"=>
					segbuff<="00000111";--7
				when "1000"=>
					segbuff<="01111111";--8
				when "1001"=>
					segbuff<="01101111";--9
				when "1010"=>
					segbuff<="01110111";--A
				when "1011"=>
					segbuff<="01111100";--B
				when "1100"=>
					segbuff<="00111001";--C
				when "1101"=>
					segbuff<="01011110";--D
				when "1110"=>
					segbuff<="01111001";--E
				when "1111"=>
					segbuff<="01110001";--F
				when others=>
					segbuff<="00000000";--none
				end case;
		end process;
--display circle
	process(clk)
	variable dig_cnt:integer range 0 to 5;
	variable stay_cnt:integer range 0 to 2;
	begin
		if clk'event and clk='1' then
			if stay_cnt=2 then
				stay_cnt:=0;
	        	case dig_cnt is
				when 0=>
					digit<="000001";
					temp_seg<=temp_r_l;
					dig_cnt:=dig_cnt+1;
				when 1=>
					digit<="000010";
					temp_seg<=temp_r_h;
					dig_cnt:=dig_cnt+1;
				when 2=>
					digit<="000100";
					temp_seg<=temp_m_l;
					dig_cnt:=dig_cnt+1;
				when 3=>
					digit<="001000";
					temp_seg<=temp_m_h;
					dig_cnt:=dig_cnt+1;
				when 4=>
					digit<="010000";
					temp_seg<=temp_l_l;
					dig_cnt:=dig_cnt+1;
				when 5=>
					digit<="100000";
					temp_seg<=temp_l_h;
					dig_cnt:=0;
				when others=>dig_cnt:=0;
				end case;
			else
				stay_cnt:=stay_cnt+1;
			end if;		
		end if;
	end process;
end arc;